<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30234">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwell: implement RMRR ACPI table<br><br>Modeled after Skylake implementation; use intel common SA<br>functions to get RMRR addresses<br><br>Test: build/boot google/samus, observe IOMMU fully functional<br>with intel_iommu=on kernel parameter<br><br>Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/broadwell/Kconfig<br>M src/soc/intel/broadwell/acpi.c<br>M src/soc/intel/broadwell/include/soc/systemagent.h<br>3 files changed, 14 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30234/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig</span><br><span>index e6cbd95..e9ec036 100644</span><br><span>--- a/src/soc/intel/broadwell/Kconfig</span><br><span>+++ b/src/soc/intel/broadwell/Kconfig</span><br><span>@@ -36,6 +36,8 @@</span><br><span> select UDELAY_TSC</span><br><span> select SOC_INTEL_COMMON</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> select HAVE_SPI_CONSOLE_SUPPORT</span><br><span> select CPU_INTEL_COMMON</span><br><span>diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c</span><br><span>index 9c6bd9b..5a30d66 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi.c</span><br><span>+++ b/src/soc/intel/broadwell/acpi.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> #include <cpu/x86/tsc.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span> #include <vendorcode/google/chromeos/gnvs.h></span><br><span> #include <soc/acpi.h></span><br><span> #include <soc/cpu.h></span><br><span>@@ -590,12 +591,20 @@</span><br><span> /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */</span><br><span> if (igfx_dev && igfx_dev->enabled && gfxvtbar</span><br><span> && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long tmp = current;</span><br><span> </span><br><span> current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);</span><br><span> current += acpi_create_dmar_ds_pci(current, 0, 2, 0);</span><br><span> </span><br><span> acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Add RMRR entry */</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_rmrr(current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ sa_get_gsm_base(), sa_get_tolud_base() - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_rmrr_fixup(tmp, current);</span><br><span> }</span><br><span> </span><br><span> /* VTVC0BAR has to be set, enabled, and in 32-bit space */</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>index 92e79cc..72601fc 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>@@ -94,9 +94,11 @@</span><br><span> </span><br><span> /* MCHBAR */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MCHBAR32</span><br><span> #define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))</span><br><span> #define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x))</span><br><span> #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> #define MCHBAR_PEI_VERSION 0x5034</span><br><span> #define BIOS_RESET_CPL 0x5da8</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30234">change 30234</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d </div>
<div style="display:none"> Gerrit-Change-Number: 30234 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>