[coreboot-gerrit] Change in ...coreboot[master]: drivers/generic: Add PCIe bridge helper

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30215 )

Change subject: drivers/generic: Add PCIe bridge helper
......................................................................


Patch Set 4:

(4 comments)

Do you really need this in all its complexity? Many things seem overkill and the ramstage part doesn't fit into our current driver model.

https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c 
File src/drivers/generic/temp_pcie_bridge/bridge_rom.c:

https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@28 
PS4, Line 28: 	outl(reg_2_cf8(dev, reg), 0xCF8);
back to the early 2000s? why not use the existing access functions?


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@66 
PS4, Line 66: 		value &= start;
potentially aligns `start` down


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@79 
PS4, Line 79: 	pci_write32(dev, TEMP_BASE(number), value);
missing write to upper part of potential 64-bit resource


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@80 
PS4, Line 80: 	command |= PCI_COMMAND_MASTER;
wtf? did I miss something and this is required for host initiated i/o?



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaec1fcc4f8db8c3b4cfd3786d3ff589dc9cb22f5
Gerrit-Change-Number: 30215
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: Daniel Kurtz <djkurtz at google.com>
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Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
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Gerrit-Comment-Date: Fri, 14 Dec 2018 22:08:37 +0000
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