[coreboot-gerrit] Change in ...coreboot[master]: mb/gigabyte/m57sli: Add mainboard
build bot (Jenkins) (Code Review)
gerrit at coreboot.org
Fri Dec 14 22:27:39 CET 2018
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27618 )
Change subject: mb/gigabyte/m57sli: Add mainboard
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Patch Set 4:
(51 comments)
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c
File src/mainboard/gigabyte/m57sli/acpi_tables.c:
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c@55
PS4, Line 55: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c@65
PS4, Line 65: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/get_bus_conf.c
File src/mainboard/gigabyte/m57sli/get_bus_conf.c:
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/get_bus_conf.c@109
PS4, Line 109: m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c
File src/mainboard/gigabyte/m57sli/mptable.c:
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@72
PS4, Line 72: m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@75
PS4, Line 75: m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@78
PS4, Line 78: m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@81
PS4, Line 81: m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@84
PS4, Line 84: m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@86
PS4, Line 86: m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@88
PS4, Line 88: m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@91
PS4, Line 91: m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@93
PS4, Line 93: m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@100
PS4, Line 100: MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@108
PS4, Line 108: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@110
PS4, Line 110: m->apicid_mcp55, 0x10 + (2 + i + j) % 4);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c
File src/mainboard/gigabyte/m57sli/resourcemap.c:
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@21
PS4, Line 21: /* Careful set limit registers before base registers which contain the enables */
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@42
PS4, Line 42: * specifies the values of A[14:12] to use with interleave enable.
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@45
PS4, Line 45: * This field defines the upper address bits of a 40 bit address
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@48
PS4, Line 48: // PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, Need for CAR with FAM10
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@81
PS4, Line 81: * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@84
PS4, Line 84: * This field defines the upper address bits of a 40-bit address
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@87
PS4, Line 87: // PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, need for CAR with FAM10
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@125
PS4, Line 125: * This field defines the upp address bits of a 40-bit address that
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@160
PS4, Line 160: * This field defines the upper address bits of a 40bit address
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@216
PS4, Line 216: * 1 = matches all address < 64K and where A[9:0] is in the
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@217
PS4, Line 217: * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@220
PS4, Line 220: * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@264
PS4, Line 264: * This field defines the lowest bus number in configuration region i
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@266
PS4, Line 266: * This field defines the highest bus number in configuration region i
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@268
PS4, Line 268: // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c
File src/mainboard/gigabyte/m57sli/romstage.c:
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@71
PS4, Line 71: #define MCP55_MB_SETUP \
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@72
PS4, Line 72: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@73
PS4, Line 73: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@74
PS4, Line 74: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@75
PS4, Line 75: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@76
PS4, Line 76: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@77
PS4, Line 77: RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 60, 0x00, 0x60,/* GPIO61 FANCTL1 */
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@87
PS4, Line 87: byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0x7b);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@89
PS4, Line 89: pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0x7b, byte);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@91
PS4, Line 91: dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa0);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@93
PS4, Line 93: pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa0, dword);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@95
PS4, Line 95: dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa4);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@97
PS4, Line 97: pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa4, dword);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@104
PS4, Line 104: static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@136
PS4, Line 136: printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@225
PS4, Line 225: * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@226
PS4, Line 226: * swap list. The first part of the list controls the BUID assignment and the
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@227
PS4, Line 227: * second part of the list provides the device to device linking. Device orientation
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@228
PS4, Line 228: * can be detected automatically, or explicitly. See documentation for more details.
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@230
PS4, Line 230: * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
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https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@241
PS4, Line 241: /* If the BUID was adjusted in early_ht we need to do the manual override */
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I20a437f6952d9f919ad186d4862ca00853d9ebca
Gerrit-Change-Number: 27618
Gerrit-PatchSet: 4
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Fri, 14 Dec 2018 21:27:39 +0000
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