<p><a href="https://review.coreboot.org/c/coreboot/+/27618">View Change</a></p><p>51 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c">File src/mainboard/gigabyte/m57sli/acpi_tables.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c@55">Patch Set #4, Line 55:</a> <code style="font-family:monospace,monospace"> current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/acpi_tables.c@65">Patch Set #4, Line 65:</a> <code style="font-family:monospace,monospace"> current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/get_bus_conf.c">File src/mainboard/gigabyte/m57sli/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/get_bus_conf.c@109">Patch Set #4, Line 109:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c">File src/mainboard/gigabyte/m57sli/mptable.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@72">Patch Set #4, Line 72:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@75">Patch Set #4, Line 75:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@78">Patch Set #4, Line 78:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@81">Patch Set #4, Line 81:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@84">Patch Set #4, Line 84:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@86">Patch Set #4, Line 86:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@88">Patch Set #4, Line 88:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@91">Patch Set #4, Line 91:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@93">Patch Set #4, Line 93:</a> <code style="font-family:monospace,monospace"> m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@100">Patch Set #4, Line 100:</a> <code style="font-family:monospace,monospace"> MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@108">Patch Set #4, Line 108:</a> <code style="font-family:monospace,monospace"> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/mptable.c@110">Patch Set #4, Line 110:</a> <code style="font-family:monospace,monospace"> m->apicid_mcp55, 0x10 + (2 + i + j) % 4);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c">File src/mainboard/gigabyte/m57sli/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@21">Patch Set #4, Line 21:</a> <code style="font-family:monospace,monospace"> /* Careful set limit registers before base registers which contain the enables */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@42">Patch Set #4, Line 42:</a> <code style="font-family:monospace,monospace"> * specifies the values of A[14:12] to use with interleave enable.</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@45">Patch Set #4, Line 45:</a> <code style="font-family:monospace,monospace"> * This field defines the upper address bits of a 40 bit address</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@48">Patch Set #4, Line 48:</a> <code style="font-family:monospace,monospace">// PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, Need for CAR with FAM10</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@81">Patch Set #4, Line 81:</a> <code style="font-family:monospace,monospace"> * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@84">Patch Set #4, Line 84:</a> <code style="font-family:monospace,monospace"> * This field defines the upper address bits of a 40-bit address</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@87">Patch Set #4, Line 87:</a> <code style="font-family:monospace,monospace">// PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, need for CAR with FAM10</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@125">Patch Set #4, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@160">Patch Set #4, Line 160:</a> <code style="font-family:monospace,monospace"> * This field defines the upper address bits of a 40bit address</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@216">Patch Set #4, Line 216:</a> <code style="font-family:monospace,monospace"> * 1 = matches all address < 64K and where A[9:0] is in the</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@217">Patch Set #4, Line 217:</a> <code style="font-family:monospace,monospace"> * range 3B0-3BB or 3C0-3DF independen of the base & limit registers</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@220">Patch Set #4, Line 220:</a> <code style="font-family:monospace,monospace"> * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@264">Patch Set #4, Line 264:</a> <code style="font-family:monospace,monospace"> * This field defines the lowest bus number in configuration region i</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@266">Patch Set #4, Line 266:</a> <code style="font-family:monospace,monospace"> * This field defines the highest bus number in configuration region i</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/resourcemap.c@268">Patch Set #4, Line 268:</a> <code style="font-family:monospace,monospace">// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c">File src/mainboard/gigabyte/m57sli/romstage.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@71">Patch Set #4, Line 71:</a> <code style="font-family:monospace,monospace">#define MCP55_MB_SETUP \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Macros with complex values should be enclosed in parentheses</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@72">Patch Set #4, Line 72:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@73">Patch Set #4, Line 73:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@74">Patch Set #4, Line 74:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@75">Patch Set #4, Line 75:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@76">Patch Set #4, Line 76:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@77">Patch Set #4, Line 77:</a> <code style="font-family:monospace,monospace"> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 60, 0x00, 0x60,/* GPIO61 FANCTL1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@87">Patch Set #4, Line 87:</a> <code style="font-family:monospace,monospace"> byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0x7b);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@89">Patch Set #4, Line 89:</a> <code style="font-family:monospace,monospace"> pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0x7b, byte);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@91">Patch Set #4, Line 91:</a> <code style="font-family:monospace,monospace"> dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa0);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@93">Patch Set #4, Line 93:</a> <code style="font-family:monospace,monospace"> pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa0, dword);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@95">Patch Set #4, Line 95:</a> <code style="font-family:monospace,monospace"> dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa4);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@97">Patch Set #4, Line 97:</a> <code style="font-family:monospace,monospace"> pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1 , 0), 0xa4, dword);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that ',' (ctx:WxW)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@104">Patch Set #4, Line 104:</a> <code style="font-family:monospace,monospace"> static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@136">Patch Set #4, Line 136:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@225">Patch Set #4, Line 225:</a> <code style="font-family:monospace,monospace"> * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@226">Patch Set #4, Line 226:</a> <code style="font-family:monospace,monospace"> * swap list. The first part of the list controls the BUID assignment and the</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@227">Patch Set #4, Line 227:</a> <code style="font-family:monospace,monospace"> * second part of the list provides the device to device linking. Device orientation</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@228">Patch Set #4, Line 228:</a> <code style="font-family:monospace,monospace"> * can be detected automatically, or explicitly. See documentation for more details.</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@230">Patch Set #4, Line 230:</a> <code style="font-family:monospace,monospace"> * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27618/4/src/mainboard/gigabyte/m57sli/romstage.c@241">Patch Set #4, Line 241:</a> <code style="font-family:monospace,monospace"> /* If the BUID was adjusted in early_ht we need to do the manual override */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/27618">change 27618</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/27618"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I20a437f6952d9f919ad186d4862ca00853d9ebca </div>
<div style="display:none"> Gerrit-Change-Number: 27618 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Fri, 14 Dec 2018 21:27:39 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
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<div style="display:none"> Gerrit-MessageType: comment </div>