[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common/block/lpc: create lpc_get_device() helper function
Subrata Banik (Code Review)
gerrit at coreboot.org
Thu Dec 13 09:45:31 CET 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30209
Change subject: soc/intel/common/block/lpc: create lpc_get_device() helper function
......................................................................
soc/intel/common/block/lpc: create lpc_get_device() helper function
This patch removes redundent declaration of pci device structure in
every function by adding lpc_get_device() helper function.
Change-Id: I84a6102bf3849e9d4fe28e4c6a11bc7badcf5114
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/block/lpc/lpc_lib.c
1 file changed, 44 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30209/1
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index bcbd8e6..409614e 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -15,8 +15,6 @@
* GNU General Public License for more details.
*/
-#define __SIMPLE_DEVICE__
-
#include <assert.h>
#include <console/console.h>
#include <device/pci.h>
@@ -25,13 +23,37 @@
#include "lpc_def.h"
#include <soc/pci_devs.h>
+#if defined(__SIMPLE_DEVICE__)
+static pci_devfn_t lpc_get_device(void)
+{
+ int devfn = PCH_DEVFN_LPC;
+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+ if (dev == PCI_DEV_INVALID)
+ die("PCH_DEV_LPC not found!\n");
+
+ return dev;
+}
+#else
+static struct device *lpc_get_device(void)
+{
+ struct device *dev = PCH_DEV_LPC;
+ if (!dev)
+ die("PCH_DEV_LPC not found!\n");
+
+ return dev;
+}
+#endif
+
+#define LPC_GET_DEV lpc_get_device()
+
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
{
uint16_t reg_io_enables;
- reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
+ reg_io_enables = pci_read_config16(LPC_GET_DEV, LPC_IO_ENABLES);
io_enables |= reg_io_enables;
- pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
+ pci_write_config16(LPC_GET_DEV, LPC_IO_ENABLES, io_enables);
return io_enables;
}
@@ -46,7 +68,7 @@
uint32_t lgir;
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
- lgir = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i));
+ lgir = pci_read_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i));
if (!(lgir & LPC_LGIR_EN))
return i;
@@ -60,7 +82,7 @@
size_t i;
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++)
- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), 0);
+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i), 0);
}
void lpc_open_pmio_window(uint16_t base, uint16_t size)
@@ -89,7 +111,7 @@
/* Skip programming if same range already programmed. */
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
- if (lgir == pci_read_config32(PCH_DEV_LPC,
+ if (lgir == pci_read_config32(LPC_GET_DEV,
LPC_GENERIC_IO_RANGE(i)))
return;
}
@@ -104,7 +126,7 @@
}
lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
- pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
+ pci_write_config32(LPC_GET_DEV, lgir_reg_offset, lgir);
printk(BIOS_DEBUG,
"LPC: Opened IO window LGIR%d: base %llx size %x\n",
@@ -119,7 +141,7 @@
{
uint32_t lgmr;
- lgmr = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE);
+ lgmr = pci_read_config32(LPC_GET_DEV, LPC_GENERIC_MEM_RANGE);
if (lgmr & LPC_LGMR_EN) {
printk(BIOS_ERR,
@@ -137,7 +159,7 @@
lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;
- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_MEM_RANGE, lgmr);
}
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
@@ -167,22 +189,17 @@
*/
static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
{
-#if defined(__SIMPLE_DEVICE__)
- pci_devfn_t dev = PCH_DEV_LPC;
-#else
- struct device *dev = PCH_DEV_LPC;
-#endif
uint8_t bc_cntl;
assert(IS_POWER_OF_2(bios_cntl_bit));
- bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
+ bc_cntl = pci_read_config8(LPC_GET_DEV, LPC_BIOS_CNTL);
bc_cntl |= bios_cntl_bit;
- pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl);
+ pci_write_config8(LPC_GET_DEV, LPC_BIOS_CNTL, bc_cntl);
/*
* Ensure an additional read back after performing lock down
*/
- pci_read_config8(PCH_DEV_LPC, LPC_BIOS_CNTL);
+ pci_read_config8(LPC_GET_DEV, LPC_BIOS_CNTL);
}
/*
@@ -214,14 +231,9 @@
*/
void lpc_set_serirq_mode(enum serirq_mode mode)
{
-#if defined(__SIMPLE_DEVICE__)
- pci_devfn_t dev = PCH_DEV_LPC;
-#else
- struct device *dev = PCH_DEV_LPC;
-#endif
uint8_t scnt;
- scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);
+ scnt = pci_read_config8(LPC_GET_DEV, LPC_SERIRQ_CTL);
scnt &= ~(LPC_SCNT_EN | LPC_SCNT_MODE);
switch (mode) {
@@ -236,7 +248,7 @@
break;
}
- pci_write_config8(dev, LPC_SERIRQ_CTL, scnt);
+ pci_write_config8(LPC_GET_DEV, LPC_SERIRQ_CTL, scnt);
}
@@ -253,7 +265,7 @@
}
/* Setup I/O Decode Range Register for LPC */
- pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
+ pci_write_config16(LPC_GET_DEV, LPC_IO_DECODE, com_ranges);
/* Enable ComA and ComB Port */
lpc_enable_fixed_io_ranges(com_enable);
}
@@ -265,21 +277,10 @@
/* Set in PCI generic decode range registers */
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++)
- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i),
gen_io_dec[i]);
}
-static void pch_lpc_interrupt_init(void)
-{
- const struct device *dev;
-
- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
- if (!dev || !dev->chip_info)
- return;
-
- soc_pch_pirq_init(dev);
-}
-
void pch_enable_lpc(void)
{
/* Lookup device tree in romstage */
@@ -294,16 +295,17 @@
lpc_set_gen_decode_range(gen_io_dec);
soc_setup_dmi_pcr_io_dec(gen_io_dec);
if (ENV_RAMSTAGE)
- pch_lpc_interrupt_init();
+ soc_pch_pirq_init(dev);
}
void lpc_enable_pci_clk_cntl(void)
{
- pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
+ pci_write_config8(LPC_GET_DEV, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
}
void lpc_disable_clkrun(void)
{
- const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);
- pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
+ const uint8_t pcctl = pci_read_config8(LPC_GET_DEV, LPC_PCCTL);
+ pci_write_config8(LPC_GET_DEV, LPC_PCCTL,
+ pcctl & ~LPC_PCCTL_CLKRUN_EN);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I84a6102bf3849e9d4fe28e4c6a11bc7badcf5114
Gerrit-Change-Number: 30209
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-MessageType: newchange
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