<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30209">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/lpc: create lpc_get_device() helper function<br><br>This patch removes redundent declaration of pci device structure in<br>every function by adding lpc_get_device() helper function.<br><br>Change-Id: I84a6102bf3849e9d4fe28e4c6a11bc7badcf5114<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>1 file changed, 44 insertions(+), 42 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30209/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>index bcbd8e6..409614e 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>@@ -15,8 +15,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <assert.h></span><br><span> #include <console/console.h></span><br><span> #include <device/pci.h></span><br><span>@@ -25,13 +23,37 @@</span><br><span> #include "lpc_def.h"</span><br><span> #include <soc/pci_devs.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+static pci_devfn_t lpc_get_device(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = PCH_DEVFN_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == PCI_DEV_INVALID)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("PCH_DEV_LPC not found!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *lpc_get_device(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("PCH_DEV_LPC not found!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_GET_DEV lpc_get_device()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)</span><br><span> {</span><br><span> uint16_t reg_io_enables;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_io_enables = pci_read_config16(LPC_GET_DEV, LPC_IO_ENABLES);</span><br><span> io_enables |= reg_io_enables;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_GET_DEV, LPC_IO_ENABLES, io_enables);</span><br><span> </span><br><span> return io_enables;</span><br><span> }</span><br><span>@@ -46,7 +68,7 @@</span><br><span> uint32_t lgir;</span><br><span> </span><br><span> for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- lgir = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i));</span><br><span style="color: hsl(120, 100%, 40%);">+ lgir = pci_read_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i));</span><br><span> </span><br><span> if (!(lgir & LPC_LGIR_EN))</span><br><span> return i;</span><br><span>@@ -60,7 +82,7 @@</span><br><span> size_t i;</span><br><span> </span><br><span> for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i), 0);</span><br><span> }</span><br><span> </span><br><span> void lpc_open_pmio_window(uint16_t base, uint16_t size)</span><br><span>@@ -89,7 +111,7 @@</span><br><span> </span><br><span> /* Skip programming if same range already programmed. */</span><br><span> for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (lgir == pci_read_config32(PCH_DEV_LPC,</span><br><span style="color: hsl(120, 100%, 40%);">+ if (lgir == pci_read_config32(LPC_GET_DEV,</span><br><span> LPC_GENERIC_IO_RANGE(i)))</span><br><span> return;</span><br><span> }</span><br><span>@@ -104,7 +126,7 @@</span><br><span> }</span><br><span> lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_GET_DEV, lgir_reg_offset, lgir);</span><br><span> </span><br><span> printk(BIOS_DEBUG,</span><br><span> "LPC: Opened IO window LGIR%d: base %llx size %x\n",</span><br><span>@@ -119,7 +141,7 @@</span><br><span> {</span><br><span> uint32_t lgmr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- lgmr = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE);</span><br><span style="color: hsl(120, 100%, 40%);">+ lgmr = pci_read_config32(LPC_GET_DEV, LPC_GENERIC_MEM_RANGE);</span><br><span> </span><br><span> if (lgmr & LPC_LGMR_EN) {</span><br><span> printk(BIOS_ERR,</span><br><span>@@ -137,7 +159,7 @@</span><br><span> </span><br><span> lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_MEM_RANGE, lgmr);</span><br><span> }</span><br><span> </span><br><span> bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)</span><br><span>@@ -167,22 +189,17 @@</span><br><span> */</span><br><span> static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> uint8_t bc_cntl;</span><br><span> </span><br><span> assert(IS_POWER_OF_2(bios_cntl_bit));</span><br><span style="color: hsl(0, 100%, 40%);">- bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ bc_cntl = pci_read_config8(LPC_GET_DEV, LPC_BIOS_CNTL);</span><br><span> bc_cntl |= bios_cntl_bit;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_GET_DEV, LPC_BIOS_CNTL, bc_cntl);</span><br><span> </span><br><span> /*</span><br><span> * Ensure an additional read back after performing lock down</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config8(PCH_DEV_LPC, LPC_BIOS_CNTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config8(LPC_GET_DEV, LPC_BIOS_CNTL);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>@@ -214,14 +231,9 @@</span><br><span> */</span><br><span> void lpc_set_serirq_mode(enum serirq_mode mode)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> uint8_t scnt;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ scnt = pci_read_config8(LPC_GET_DEV, LPC_SERIRQ_CTL);</span><br><span> scnt &= ~(LPC_SCNT_EN | LPC_SCNT_MODE);</span><br><span> </span><br><span> switch (mode) {</span><br><span>@@ -236,7 +248,7 @@</span><br><span> break;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_SERIRQ_CTL, scnt);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_GET_DEV, LPC_SERIRQ_CTL, scnt);</span><br><span> }</span><br><span> </span><br><span> </span><br><span>@@ -253,7 +265,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Setup I/O Decode Range Register for LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_GET_DEV, LPC_IO_DECODE, com_ranges);</span><br><span> /* Enable ComA and ComB Port */</span><br><span> lpc_enable_fixed_io_ranges(com_enable);</span><br><span> }</span><br><span>@@ -265,21 +277,10 @@</span><br><span> </span><br><span> /* Set in PCI generic decode range registers */</span><br><span> for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_GET_DEV, LPC_GENERIC_IO_RANGE(i),</span><br><span> gen_io_dec[i]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_interrupt_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev || !dev->chip_info)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- soc_pch_pirq_init(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span> /* Lookup device tree in romstage */</span><br><span>@@ -294,16 +295,17 @@</span><br><span> lpc_set_gen_decode_range(gen_io_dec);</span><br><span> soc_setup_dmi_pcr_io_dec(gen_io_dec);</span><br><span> if (ENV_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_lpc_interrupt_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_pch_pirq_init(dev);</span><br><span> }</span><br><span> </span><br><span> void lpc_enable_pci_clk_cntl(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_GET_DEV, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);</span><br><span> }</span><br><span> </span><br><span> void lpc_disable_clkrun(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t pcctl = pci_read_config8(LPC_GET_DEV, LPC_PCCTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_GET_DEV, LPC_PCCTL,</span><br><span style="color: hsl(120, 100%, 40%);">+ pcctl & ~LPC_PCCTL_CLKRUN_EN);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30209">change 30209</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30209"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I84a6102bf3849e9d4fe28e4c6a11bc7badcf5114 </div>
<div style="display:none"> Gerrit-Change-Number: 30209 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>