[coreboot-gerrit] Change in ...coreboot[master]: src/cpu/intel: Set get_ia32_fsb function common

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30103


Change subject: src/cpu/intel: Set get_ia32_fsb function common
......................................................................

src/cpu/intel: Set get_ia32_fsb function common

get_ia32_fsb will return FSB values of intel's CPUs.

Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/common/Makefile.inc
A src/cpu/intel/common/fsb.c
A src/include/cpu/intel/fsb.h
3 files changed, 88 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30103/1

diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index 1e94ec9..2fc6da9 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1 +1,5 @@
 ramstage-y += common_init.c
+romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
+smm-y += fsb.c
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
new file mode 100644
index 0000000..9195ee6
--- /dev/null
+++ b/src/cpu/intel/common/fsb.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/fsb.h>
+#include <console/console.h>
+
+int get_ia32_fsb(void)
+{
+	struct cpuinfo_x86 c;
+	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
+	int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
+	msr_t msr;
+
+	get_fms(&c, cpuid_eax(1));
+	switch (c.x86) {
+	case 0x6:
+		switch (c.x86_model) {
+		case 0xe:  /* Core Solo/Duo */
+		case 0x1c: /* Atom */
+			return core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+		case 0xf:  /* Core 2 or Xeon */
+		case 0x17: /* Enhanced Core */
+			return core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+		case 0x3c: /* Haswell BCLK fixed at 100MHz */
+		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+			return 100;
+		default:
+			printk(BIOS_WARNING,
+			"Warning: No supported FSB frequency. Assuming 200MHz\n");
+			return 200;
+		}
+	case 0xf: /* Netburst */
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+		switch (c.x86_model) {
+		case 0x2:
+			return f2x_fsb[(msr.lo >> 16) & 7];
+		case 0x3:
+		case 0x4:
+		case 0x6:
+			return core2_fsb[(msr.lo >> 16) & 7];
+		default:
+			printk(BIOS_WARNING,
+			"Warning: No supported FSB frequency. Assuming 200MHz\n");
+			return 200;
+		} /* default: fallthrough */
+	default:
+		return -1;
+	}
+}
diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h
new file mode 100644
index 0000000..8064111
--- /dev/null
+++ b/src/include/cpu/intel/fsb.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CPU_INTEL_FSB_H
+#define CPU_INTEL_FSB_H
+
+int get_ia32_fsb(void);
+
+#endif /* CPU_INTEL_FSB_H */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28
Gerrit-Change-Number: 30103
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas at noos.fr>
Gerrit-MessageType: newchange
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