<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30103">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/cpu/intel: Set get_ia32_fsb function common<br><br>get_ia32_fsb will return FSB values of intel's CPUs.<br><br>Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/common/Makefile.inc<br>A src/cpu/intel/common/fsb.c<br>A src/include/cpu/intel/fsb.h<br>3 files changed, 88 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30103/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc</span><br><span>index 1e94ec9..2fc6da9 100644</span><br><span>--- a/src/cpu/intel/common/Makefile.inc</span><br><span>+++ b/src/cpu/intel/common/Makefile.inc</span><br><span>@@ -1 +1,5 @@</span><br><span> ramstage-y += common_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += fsb.c</span><br><span>diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9195ee6</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/common/fsb.c</span><br><span>@@ -0,0 +1,65 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/speedstep.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/fsb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_ia32_fsb(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuinfo_x86 c;</span><br><span style="color: hsl(120, 100%, 40%);">+ int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };</span><br><span style="color: hsl(120, 100%, 40%);">+ int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };</span><br><span style="color: hsl(120, 100%, 40%);">+ int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_fms(&c, cpuid_eax(1));</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (c.x86) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x6:</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (c.x86_model) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xe: /* Core Solo/Duo */</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x1c: /* Atom */</span><br><span style="color: hsl(120, 100%, 40%);">+ return core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xf: /* Core 2 or Xeon */</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x17: /* Enhanced Core */</span><br><span style="color: hsl(120, 100%, 40%);">+ return core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x3c: /* Haswell BCLK fixed at 100MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+ return 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Warning: No supported FSB frequency. Assuming 200MHz\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 200;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xf: /* Netburst */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_EBC_FREQUENCY_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (c.x86_model) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return f2x_fsb[(msr.lo >> 16) & 7];</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x3:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x4:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x6:</span><br><span style="color: hsl(120, 100%, 40%);">+ return core2_fsb[(msr.lo >> 16) & 7];</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Warning: No supported FSB frequency. Assuming 200MHz\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 200;</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* default: fallthrough */</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..8064111</span><br><span>--- /dev/null</span><br><span>+++ b/src/include/cpu/intel/fsb.h</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CPU_INTEL_FSB_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPU_INTEL_FSB_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_ia32_fsb(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* CPU_INTEL_FSB_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30103">change 30103</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 </div>
<div style="display:none"> Gerrit-Change-Number: 30103 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>