[coreboot-gerrit] Change in ...coreboot[master]: google/sarien: Increase BIOS region to 28MB

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29945 )

Change subject: google/sarien: Increase BIOS region to 28MB
......................................................................

google/sarien: Increase BIOS region to 28MB

Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.

BUG=b:119267832
TEST=Build and boot fine on sarien platform.

Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved



diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 6631769..ef97ab8 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -1,11 +1,11 @@
 FLASH at 0xfe000000 0x2000000 {
-	SI_ALL at 0x0 0x1000000 {
+	SI_ALL at 0x0 0x400000 {
 		SI_DESC at 0x0 0x1000
 		SI_EC at 0x1000 0x100000
 		SI_GBE at 0x101000 0x2000
-		SI_ME at 0x103000 0xefd000
+		SI_ME at 0x103000 0x2fd000
 	}
-	SI_BIOS at 0x1000000 0x1000000 {
+	SI_BIOS at 0x400000 0x1c00000 {
 		RW_SECTION_A at 0x0 0x280000 {
 			VBLOCK_A at 0x0 0x10000
 			FW_MAIN_A(CBFS)@0x10000 0x26ffc0
@@ -30,8 +30,8 @@
 			RW_NVRAM at 0x2a000 0x6000
 		}
 		CONSOLE at 0x530000 0x20000
-		RW_LEGACY(CBFS)@0x550000 0x6b0000
-		WP_RO at 0xc00000 0x400000 {
+		RW_LEGACY(CBFS)@0x550000 0x12b0000
+		WP_RO at 0x1800000 0x400000 {
 			RO_VPD at 0x0 0x4000
 			RO_UNUSED at 0x4000 0xc000
 			RO_SECTION at 0x10000 0x3f0000 {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Gerrit-Change-Number: 29945
Gerrit-PatchSet: 3
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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