<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29945">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Duncan Laurie: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/sarien: Increase BIOS region to 28MB<br><br>Platform have a 32MB SPI chip, so we can increase the bios region from<br>16MB to 28MB.<br><br>BUG=b:119267832<br>TEST=Build and boot fine on sarien platform.<br><br>Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Reviewed-on: https://review.coreboot.org/c/29945<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/mainboard/google/sarien/chromeos.fmd<br>1 file changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd</span><br><span>index 6631769..ef97ab8 100644</span><br><span>--- a/src/mainboard/google/sarien/chromeos.fmd</span><br><span>+++ b/src/mainboard/google/sarien/chromeos.fmd</span><br><span>@@ -1,11 +1,11 @@</span><br><span> FLASH@0xfe000000 0x2000000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ALL@0x0 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x400000 {</span><br><span> SI_DESC@0x0 0x1000</span><br><span> SI_EC@0x1000 0x100000</span><br><span> SI_GBE@0x101000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ME@0x103000 0xefd000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ME@0x103000 0x2fd000</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- SI_BIOS@0x1000000 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_BIOS@0x400000 0x1c00000 {</span><br><span> RW_SECTION_A@0x0 0x280000 {</span><br><span> VBLOCK_A@0x0 0x10000</span><br><span> FW_MAIN_A(CBFS)@0x10000 0x26ffc0</span><br><span>@@ -30,8 +30,8 @@</span><br><span> RW_NVRAM@0x2a000 0x6000</span><br><span> }</span><br><span> CONSOLE@0x530000 0x20000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_LEGACY(CBFS)@0x550000 0x6b0000</span><br><span style="color: hsl(0, 100%, 40%);">- WP_RO@0xc00000 0x400000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_LEGACY(CBFS)@0x550000 0x12b0000</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x1800000 0x400000 {</span><br><span> RO_VPD@0x0 0x4000</span><br><span> RO_UNUSED@0x4000 0xc000</span><br><span> RO_SECTION@0x10000 0x3f0000 {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29945">change 29945</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29945"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 </div>
<div style="display:none"> Gerrit-Change-Number: 29945 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>