[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add DPTF ACPI code

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29759 )

Change subject: soc/intel/cannonlake: Add DPTF ACPI code
......................................................................

soc/intel/cannonlake: Add DPTF ACPI code

Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code.  For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.

Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie at google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan at google.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
A src/soc/intel/cannonlake/acpi/dptf.asl
1 file changed, 45 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl
new file mode 100644
index 0000000..098a61c
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/dptf.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_DEVICE		B0D4
+#define DPTF_CPU_ADDR		0x00040000
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE	80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1	80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2	70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3	60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4	50
+#endif

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Gerrit-Change-Number: 29759
Gerrit-PatchSet: 3
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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