<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29759">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add DPTF ACPI code<br><br>Define the constants that DPTF expects from the SOC in order to<br>use the common DPTF ACPI code. For cannonlake this indicates<br>the CPU device is called B0D4 and is at PCI address 00:04.0.<br><br>Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>Reviewed-on: https://review.coreboot.org/c/29759<br>Reviewed-by: Furquan Shaikh <furquan@google.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>A src/soc/intel/cannonlake/acpi/dptf.asl<br>1 file changed, 45 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..098a61c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/dptf.asl</span><br><span>@@ -0,0 +1,45 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_DEVICE B0D4</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ADDR 0x00040000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_PASSIVE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_CRITICAL</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_ACTIVE_AC0</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ACTIVE_AC0 90</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_ACTIVE_AC1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ACTIVE_AC1 80</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_ACTIVE_AC2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ACTIVE_AC2 70</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_ACTIVE_AC3</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ACTIVE_AC3 60</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DPTF_CPU_ACTIVE_AC4</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_ACTIVE_AC4 50</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29759">change 29759</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 </div>
<div style="display:none"> Gerrit-Change-Number: 29759 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>