[coreboot-gerrit] Change in ...coreboot[master]: riscv: optimize smp_pause

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30032


Change subject: riscv: optimize smp_pause
......................................................................

riscv: optimize smp_pause

Optimize smp_pause to prevent modification of the exception control register.

Change-Id: Ib5ab683bc4c96fd8a32768d49ad4ebf8cab1d1a6
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/smp.c
1 file changed, 6 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30032/1

diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 8d07d39..746c4cb 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -34,8 +34,8 @@
 			barrier();
 		} while (SYNCA != 0x01234567);
 
-		clear_csr(mstatus, MSTATUS_MIE);
-		write_csr(mie, MIP_MSIP);
+		uintptr_t bkp_mstatus = clear_csr(mstatus, MSTATUS_MIE);
+		uintptr_t bkp_mie = swap_csr(mie, MIP_MSIP);
 
 		/* count how many cores enter the halt */
 		__sync_fetch_and_add(&SYNCB, 1);
@@ -45,6 +45,10 @@
 			__asm__ volatile ("wfi");
 		} while ((read_csr(mip) & MIP_MSIP) == 0);
 		set_msip(hartid, 0);
+
+		write_csr(mstatus, bkp_mstatus);
+		write_csr(mie, bkp_mie);
+
 		HLS()->entry.fn(HLS()->entry.arg);
 	} else {
 		/* Initialize the counter and

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib5ab683bc4c96fd8a32768d49ad4ebf8cab1d1a6
Gerrit-Change-Number: 30032
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-MessageType: newchange
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