<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30032">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: optimize smp_pause<br><br>Optimize smp_pause to prevent modification of the exception control register.<br><br>Change-Id: Ib5ab683bc4c96fd8a32768d49ad4ebf8cab1d1a6<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/smp.c<br>1 file changed, 6 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30032/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c</span><br><span>index 8d07d39..746c4cb 100644</span><br><span>--- a/src/arch/riscv/smp.c</span><br><span>+++ b/src/arch/riscv/smp.c</span><br><span>@@ -34,8 +34,8 @@</span><br><span>                  barrier();</span><br><span>           } while (SYNCA != 0x01234567);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-              clear_csr(mstatus, MSTATUS_MIE);</span><br><span style="color: hsl(0, 100%, 40%);">-                write_csr(mie, MIP_MSIP);</span><br><span style="color: hsl(120, 100%, 40%);">+             uintptr_t bkp_mstatus = clear_csr(mstatus, MSTATUS_MIE);</span><br><span style="color: hsl(120, 100%, 40%);">+              uintptr_t bkp_mie = swap_csr(mie, MIP_MSIP);</span><br><span> </span><br><span>             /* count how many cores enter the halt */</span><br><span>            __sync_fetch_and_add(&SYNCB, 1);</span><br><span>@@ -45,6 +45,10 @@</span><br><span>                    __asm__ volatile ("wfi");</span><br><span>          } while ((read_csr(mip) & MIP_MSIP) == 0);</span><br><span>               set_msip(hartid, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+                write_csr(mstatus, bkp_mstatus);</span><br><span style="color: hsl(120, 100%, 40%);">+              write_csr(mie, bkp_mie);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>           HLS()->entry.fn(HLS()->entry.arg);</span><br><span>     } else {</span><br><span>             /* Initialize the counter and</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30032">change 30032</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30032"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ib5ab683bc4c96fd8a32768d49ad4ebf8cab1d1a6 </div>
<div style="display:none"> Gerrit-Change-Number: 30032 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>