[coreboot-gerrit] Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29908 )

Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
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Patch Set 2: Code-Review-1

This patch leads to a non booting board.
It hangs somewhere in imd_create_empty() which is called form romstage_main_continue() by the line

cbmem_was_initted = !cbmem_recovery(0);

in romstage.c (last postcode is 0x4d).
I haven't dug that deep due to time constraints but it looks like the cache-as-ram memory space is not available anymore (which is the case for broadwell-de in romstage_main_continue) while it is still used by the cbmem-code. Let me know if you need further tests.


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9
Gerrit-Change-Number: 29908
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Huang Jin <huang.jin at intel.com>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
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Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
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Gerrit-Comment-Date: Tue, 04 Dec 2018 06:36:45 +0000
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