[coreboot-gerrit] Change in ...coreboot[master]: cpu/x86/lapic: Link apic_timer.c into SMM

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30020


Change subject: cpu/x86/lapic: Link apic_timer.c into SMM
......................................................................

cpu/x86/lapic: Link apic_timer.c into SMM

This provides udelay() and a monotonic timer to SMM.
Also remove the custom implementation on i945.

Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/x86/lapic/Makefile.inc
M src/northbridge/intel/i945/Makefile.inc
D src/northbridge/intel/i945/udelay.c
3 files changed, 1 insertion(+), 79 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30020/1

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9454f8f..7637250 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -4,6 +4,7 @@
 romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 bootblock-y += boot_cpu.c
 verstage-y += boot_cpu.c
 romstage-y += boot_cpu.c
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index ffeabdc..fa51df7 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -27,8 +27,6 @@
 romstage-y += debug.c
 romstage-y += rcven.c
 
-smm-y += udelay.c
-
 postcar-y += ram_calc.c
 
 endif
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
deleted file mode 100644
index 8447453..0000000
--- a/src/northbridge/intel/i945/udelay.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-#include <cpu/intel/speedstep.h>
-
-/**
- * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 0, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(MSR_FSB_FREQ);
-	switch (msr.lo & 0x07) {
-	case 5:
-		fsb = 400;
-		break;
-	case 1:
-		fsb = 533;
-		break;
-	case 3:
-		fsb = 667;
-		break;
-	case 2:
-		fsb = 800;
-		break;
-	case 0:
-		fsb = 1067;
-		break;
-	case 4:
-		fsb = 1333;
-		break;
-	case 6:
-		fsb = 1600;
-		break;
-	}
-
-	msr = rdmsr(IA32_PERF_STATUS);
-	divisor = (msr.hi >> 8) & 0x1f;
-
-	d = (fsb * divisor) / 4;	/* CPU clock is always a quarter. */
-
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo))
-		tsc1.hi++;
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce
Gerrit-Change-Number: 30020
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-MessageType: newchange
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