<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30020">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/x86/lapic: Link apic_timer.c into SMM<br><br>This provides udelay() and a monotonic timer to SMM.<br>Also remove the custom implementation on i945.<br><br>Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/x86/lapic/Makefile.inc<br>M src/northbridge/intel/i945/Makefile.inc<br>D src/northbridge/intel/i945/udelay.c<br>3 files changed, 1 insertion(+), 79 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30020/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc</span><br><span>index 9454f8f..7637250 100644</span><br><span>--- a/src/cpu/x86/lapic/Makefile.inc</span><br><span>+++ b/src/cpu/x86/lapic/Makefile.inc</span><br><span>@@ -4,6 +4,7 @@</span><br><span> romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c</span><br><span> ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c</span><br><span> postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c</span><br><span> bootblock-y += boot_cpu.c</span><br><span> verstage-y += boot_cpu.c</span><br><span> romstage-y += boot_cpu.c</span><br><span>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc</span><br><span>index ffeabdc..fa51df7 100644</span><br><span>--- a/src/northbridge/intel/i945/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/i945/Makefile.inc</span><br><span>@@ -27,8 +27,6 @@</span><br><span> romstage-y += debug.c</span><br><span> romstage-y += rcven.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-smm-y += udelay.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> postcar-y += ram_calc.c</span><br><span> </span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c</span><br><span>deleted file mode 100644</span><br><span>index 8447453..0000000</span><br><span>--- a/src/northbridge/intel/i945/udelay.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,77 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/tsc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/speedstep.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void udelay(u32 us)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">- tsc_t tsc, tsc1, tscd;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 fsb = 0, divisor;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 d; /* ticks per us */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_FSB_FREQ);</span><br><span style="color: hsl(0, 100%, 40%);">- switch (msr.lo & 0x07) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 5:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 400;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 1:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 533;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 3:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 667;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 2:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 800;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 1067;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 4:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 1333;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 6:</span><br><span style="color: hsl(0, 100%, 40%);">- fsb = 1600;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_PERF_STATUS);</span><br><span style="color: hsl(0, 100%, 40%);">- divisor = (msr.hi >> 8) & 0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- multiply_to_tsc(&tscd, us, d);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tsc1 = rdtsc();</span><br><span style="color: hsl(0, 100%, 40%);">- dword = tsc1.lo + tscd.lo;</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dword < tsc1.lo) || (dword < tscd.lo))</span><br><span style="color: hsl(0, 100%, 40%);">- tsc1.hi++;</span><br><span style="color: hsl(0, 100%, 40%);">- tsc1.lo = dword;</span><br><span style="color: hsl(0, 100%, 40%);">- tsc1.hi += tscd.hi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- tsc = rdtsc();</span><br><span style="color: hsl(0, 100%, 40%);">- } while ((tsc.hi < tsc1.hi)</span><br><span style="color: hsl(0, 100%, 40%);">- || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30020">change 30020</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce </div>
<div style="display:none"> Gerrit-Change-Number: 30020 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>