[coreboot-gerrit] Change in coreboot[master]: src/*/intel: introduce warning when building with no IFD

Angel Pons (Code Review) gerrit at coreboot.org
Wed Aug 29 05:38:39 CEST 2018 

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28382


Change subject: src/*/intel: introduce warning when building with no IFD
......................................................................

src/*/intel: introduce warning when building with no IFD

Add a warning as suggested in patch #28233 with the
"CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option.

Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819
Signed-off-by: Angel Pons <th3fanbus at gmail.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/fsp_baytrail/Kconfig
M src/soc/intel/fsp_broadwell_de/Kconfig
M src/soc/intel/skylake/Kconfig
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/firmware/Makefile.inc
M src/southbridge/intel/fsp_bd82x6x/Kconfig
M src/southbridge/intel/fsp_i89xx/Kconfig
M src/southbridge/intel/fsp_rangeley/Kconfig
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/lynxpoint/Kconfig
16 files changed, 28 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28382/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 3e84a50..0ed8572 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -46,6 +46,7 @@
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	select GENERIC_GPIO_LIB
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_SMI_HANDLER
 	select MRC_SETTINGS_PROTECT
 	select MRC_SETTINGS_VARIABLE_DATA
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index b4dc823..9bd4c24 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -35,6 +35,7 @@
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SWSMISCI
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 607d78c..906a0c4 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -43,6 +43,7 @@
 	select UDELAY_TSC
 	select USE_GENERIC_FSP_CAR_INC
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select HAVE_FSP_GOP
 	select GENERIC_GPIO_LIB
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 32148c4..dd5548b 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -36,6 +36,7 @@
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select CPU_INTEL_COMMON
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ef39706..351f4b7 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -37,6 +37,7 @@
 	select HAVE_FSP_GOP
 	select HAVE_HARD_RESET
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 68084bc..d17598b 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -42,6 +42,7 @@
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_SPI_CONSOLE_SUPPORT
 
 	# Microcode header files are delivered in FSP package
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index cc3e6e2..08b3b0f 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -23,6 +23,7 @@
 	# Microcode header files are delivered in FSP package
 	select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SMM_TSEG
 	select HAVE_SMI_HANDLER
 	select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 9412b03..7066eb0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -33,6 +33,7 @@
 	select HAVE_FSP_GOP
 	select HAVE_HARD_RESET
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
 	select INTEL_GMA_ACPI
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index c028595..b073d26 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -38,6 +38,7 @@
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select RTC
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 4f8a407..be1203a 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -25,6 +25,11 @@
 config SOUTHBRIDGE_INTEL_COMMON_SMM
 	def_bool n
 
+config INTEL_DESCRIPTOR_MODE_REQUIRED
+	# This config states that the platform *requires* running in
+	# descriptor mode to be usable (prevent Platform Disable Wait).
+	def_bool n
+
 config INTEL_CHIPSET_LOCKDOWN
 	depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
 	#ChromeOS's payload seems to handle finalization on its on.
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
index 426863c..1b7e320 100644
--- a/src/southbridge/intel/common/firmware/Makefile.inc
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -20,9 +20,7 @@
 # that adds additional components to the final firmware
 # image outside of CBFS
 
-ifeq ($(CONFIG_HAVE_IFD_BIN),y)
 INTERMEDIATE+=add_intel_firmware
-endif
 
 IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
 ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),)
@@ -30,6 +28,7 @@
 endif
 
 add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL)
+ifeq ($(CONFIG_HAVE_IFD_BIN),y)
 	printf "    DD         Adding Intel Firmware Descriptor\n"
 	dd if=$(IFD_BIN_PATH) \
 		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
@@ -85,6 +84,14 @@
 	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
 endif
 
+else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y)
+	printf "\n\t** WARNING **\n"
+	printf "coreboot will be built without an Intel Firmware Descriptor.\n"
+	printf "Never write a complete coreboot.rom without an IFD to your\n"
+	printf "board's flash chip! You can use flashrom's IFD or layout\n"
+	printf "parameters to flash only to the BIOS region.\n\n"
+endif
+
 PHONY+=add_intel_firmware
 
 endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index 877a335..9c12d40 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -30,6 +30,7 @@
 	select PCIEXP_COMMON_CLOCK
 	select COMMON_FADT
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index d0cb45c..b899567 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -30,6 +30,7 @@
 	select PCIEXP_COMMON_CLOCK
 	select COMMON_FADT
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select NO_EARLY_BOOTBLOCK_POSTCODES
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index ab85ec4..44412c9 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -30,6 +30,7 @@
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index d377950..727c630 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -36,6 +36,7 @@
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index ee870fc..5a07b7e 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -31,6 +31,7 @@
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_REQUIRED
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819
Gerrit-Change-Number: 28382
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus at gmail.com>
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