[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Correct the Tx signal from SATA interface

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28285


Change subject: siemens/mc_apl1: Correct the Tx signal from SATA interface
......................................................................

siemens/mc_apl1: Correct the Tx signal from SATA interface

Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3.

Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28285/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index 540e322..773ca29 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -47,6 +47,12 @@
 	 * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
 	 */
 	pcr_write16(PID_ITSS, 0x314c, 0x0321);
+
+	/*
+	 * Correct the SATA transmit signal via the High Speed I/O Transmit
+	 * Control Register 3.
+	 */
+	pcr_rmw32(0xa5, 0xa8c, (0x00 << 16), (0x4a << 16));
 }
 
 static void wait_for_legacy_dev(void *unused)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4
Gerrit-Change-Number: 28285
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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