[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Disable PCI clock outputs on XIO bridge

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28284


Change subject: siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
......................................................................

siemens/mc_apl1: Disable PCI clock outputs on XIO bridge

This patch disables the unused PCI clock outputs on the XIO2001 PCI
Express to PCI Bridge.

Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/include/device/pci_ids.h
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
2 files changed, 9 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28284/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 4ced4a5..bde150f 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -782,6 +782,7 @@
 #define PCI_VENDOR_ID_TI		0x104c
 #define PCI_DEVICE_ID_TI_TVP4010	0x3d04
 #define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_XIO2001	0x8240
 #define PCI_DEVICE_ID_TI_1130		0xac12
 #define PCI_DEVICE_ID_TI_1031		0xac13
 #define PCI_DEVICE_ID_TI_1131		0xac15
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index 540e322..da01ce3 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -15,6 +15,8 @@
 
 #include <bootstate.h>
 #include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <gpio.h>
 #include <hwilib.h>
 #include <intelblocks/lpc_lib.h>
@@ -28,6 +30,7 @@
 void variant_mainboard_final(void)
 {
 	int status;
+	struct device *dev = NULL;
 
 	/*
 	 * Set up the DP2LVDS converter.
@@ -47,6 +50,11 @@
 	 * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
 	 */
 	pcr_write16(PID_ITSS, 0x314c, 0x0321);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
 }
 
 static void wait_for_legacy_dev(void *unused)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177
Gerrit-Change-Number: 28284
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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