[coreboot-gerrit] Change in coreboot[master]: mb/intel/dg43gt: Add documentation

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28258


Change subject: mb/intel/dg43gt: Add documentation
......................................................................

mb/intel/dg43gt: Add documentation

Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/intel/dg43gt.md
A Documentation/mainboard/intel/dg43gt_closeup.jpg
A Documentation/mainboard/intel/dg43gt_full.jpg
4 files changed, 101 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28258/1

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 6c75ea2..9301971 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -10,6 +10,10 @@
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
 
+## Intel
+
+- [DG43GT](intel/dg43gt.md)
+
 ## Foxconn
 
 - [D41S](foxconn/d41s.md)
diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md
new file mode 100644
index 0000000..ee970f0
--- /dev/null
+++ b/Documentation/mainboard/intel/dg43gt.md
@@ -0,0 +1,97 @@
+# Intel DG43GT
+
+This page describes how to run coreboot on the [Intel DG43GT] desktop.
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25X32     |
++---------------------+------------+
+| Size                | 4 MiB      |
++---------------------+------------+
+| In circuit flashing | NO!        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+Only the BIOS region can and needs to written to.
+
+     # flashrom -p internal --ifd -i bios -w coreboot.rom --noverify
+
+### External programming
+
+ISP (in circuit programming) seems to be impossible on this board, which
+is a property it shares wth many boards featuring the ICH10 southbridge.
+**Recovering from a bad flash will require desoldering the flash!**
+Desoldering the SPI flash can easily be done with a hot air station.
+Apply some flux around the SPI flash, set the hot air station to 350-400°C
+and after heating the chip up for a minute it should be possible to remove it.
+
+Having removed the flash chip you can reprogram and resolder it using a
+soldering iron.
+Another option would be to hook up a SPI flash (socket) to the SPI header,
+for easier flash removing in the future (if you expect to be hacking on this
+board). To do this you first need to solder the SPI header to the board.
+
+**NOTE: this header cannot be used for ISP either.**
+
+**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3V.**
+
+The layout of the header is:
+    
+```
+                  +---+---+
+           GND <- | x | x | -> SPI_CLK
+                  +---+---+
+          3VSB <- | x | x | -> SPI_MISO
+                  +---+---+
+                  |   | x | -> SPI_MOSI
+                  +---+---+
+        SPI_CS# <-| x | x | -> SPI_CS# (again)
+                  +---+---+
+```
+
+**Picture of the board with the flash hooked on externally**
+![][dg43gt_full]
+
+**Close up picture of the SPI flash pads and recovery header**
+![][dg43gt_closeup]
+
+[dg43gt_full]: dg43gt_full.jpg
+[dg43gt_closeup]: dg43gt_closeup.jpg
+
+## Technology
+
+```eval_rst
++------------------+---------------------------------------------------+
+| Northbridge      | Intel G43 (called x4x in coreboot code)           |
++------------------+---------------------------------------------------+
+| Southbridge      | Intel ICH10 (called i82801jx in coreboot code)    |
++------------------+---------------------------------------------------+
+| CPU (LGA775)     | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) |
++------------------+---------------------------------------------------+
+| SuperIO          | Windond w83627dhg                                 |
++------------------+---------------------------------------------------+
+| Coprocessor      | Intel ME (optionnaly enabled)                     |
++------------------+---------------------------------------------------+
+| Clockgen (CK505) | SLG8XP549T                                        |
++------------------+---------------------------------------------------+
+```
+
+[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/intel/dg43gt_closeup.jpg b/Documentation/mainboard/intel/dg43gt_closeup.jpg
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diff --git a/Documentation/mainboard/intel/dg43gt_full.jpg b/Documentation/mainboard/intel/dg43gt_full.jpg
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4
Gerrit-Change-Number: 28258
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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