<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28258">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/dg43gt: Add documentation<br><br>Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M Documentation/mainboard/index.md<br>A Documentation/mainboard/intel/dg43gt.md<br>A Documentation/mainboard/intel/dg43gt_closeup.jpg<br>A Documentation/mainboard/intel/dg43gt_full.jpg<br>4 files changed, 101 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28258/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index 6c75ea2..9301971 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -10,6 +10,10 @@</span><br><span> </span><br><span> - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+## Intel</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [DG43GT](intel/dg43gt.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ## Foxconn</span><br><span> </span><br><span> - [D41S](foxconn/d41s.md)</span><br><span>diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md</span><br><span>new file mode 100644</span><br><span>index 0000000..ee970f0</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/intel/dg43gt.md</span><br><span>@@ -0,0 +1,97 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Intel DG43GT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This page describes how to run coreboot on the [Intel DG43GT] desktop.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++=====================+============+</span><br><span style="color: hsl(120, 100%, 40%);">+| Socketed flash | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Model | W25X32 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Size | 4 MiB |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| In circuit flashing | NO! |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Package | SOIC-8 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Write protection | No |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Dual BIOS feature | No |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Internal flashing | yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The SPI flash can be accessed using [flashrom].</span><br><span style="color: hsl(120, 100%, 40%);">+Only the BIOS region can and needs to written to.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # flashrom -p internal --ifd -i bios -w coreboot.rom --noverify</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### External programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ISP (in circuit programming) seems to be impossible on this board, which</span><br><span style="color: hsl(120, 100%, 40%);">+is a property it shares wth many boards featuring the ICH10 southbridge.</span><br><span style="color: hsl(120, 100%, 40%);">+**Recovering from a bad flash will require desoldering the flash!**</span><br><span style="color: hsl(120, 100%, 40%);">+Desoldering the SPI flash can easily be done with a hot air station.</span><br><span style="color: hsl(120, 100%, 40%);">+Apply some flux around the SPI flash, set the hot air station to 350-400°C</span><br><span style="color: hsl(120, 100%, 40%);">+and after heating the chip up for a minute it should be possible to remove it.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Having removed the flash chip you can reprogram and resolder it using a</span><br><span style="color: hsl(120, 100%, 40%);">+soldering iron.</span><br><span style="color: hsl(120, 100%, 40%);">+Another option would be to hook up a SPI flash (socket) to the SPI header,</span><br><span style="color: hsl(120, 100%, 40%);">+for easier flash removing in the future (if you expect to be hacking on this</span><br><span style="color: hsl(120, 100%, 40%);">+board). To do this you first need to solder the SPI header to the board.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**NOTE: this header cannot be used for ISP either.**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3V.**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The layout of the header is:</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+ +---+---+</span><br><span style="color: hsl(120, 100%, 40%);">+ GND <- | x | x | -> SPI_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ +---+---+</span><br><span style="color: hsl(120, 100%, 40%);">+ 3VSB <- | x | x | -> SPI_MISO</span><br><span style="color: hsl(120, 100%, 40%);">+ +---+---+</span><br><span style="color: hsl(120, 100%, 40%);">+ | | x | -> SPI_MOSI</span><br><span style="color: hsl(120, 100%, 40%);">+ +---+---+</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_CS# <-| x | x | -> SPI_CS# (again)</span><br><span style="color: hsl(120, 100%, 40%);">+ +---+---+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Picture of the board with the flash hooked on externally**</span><br><span style="color: hsl(120, 100%, 40%);">+![][dg43gt_full]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Close up picture of the SPI flash pads and recovery header**</span><br><span style="color: hsl(120, 100%, 40%);">+![][dg43gt_closeup]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[dg43gt_full]: dg43gt_full.jpg</span><br><span style="color: hsl(120, 100%, 40%);">+[dg43gt_closeup]: dg43gt_closeup.jpg</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Northbridge | Intel G43 (called x4x in coreboot code) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Southbridge | Intel ICH10 (called i82801jx in coreboot code) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU (LGA775) | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SuperIO | Windond w83627dhg |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | Intel ME (optionnaly enabled) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Clockgen (CK505) | SLG8XP549T |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+---------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom]: https://flashrom.org/Flashrom</span><br><span>diff --git a/Documentation/mainboard/intel/dg43gt_closeup.jpg b/Documentation/mainboard/intel/dg43gt_closeup.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..c747aa8</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/intel/dg43gt_closeup.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/intel/dg43gt_full.jpg b/Documentation/mainboard/intel/dg43gt_full.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..52f3808</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/intel/dg43gt_full.jpg</span><br><span>Binary files differ</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28258">change 28258</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 </div>
<div style="display:none"> Gerrit-Change-Number: 28258 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>