[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Lijian Zhao (Code Review)
gerrit at coreboot.org
Mon Aug 20 23:18:56 CEST 2018
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28248
Change subject: soc/intel/cannonlake: Change LPDDR4 to MEMCFG
......................................................................
soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/google/zoombini/Kconfig
M src/mainboard/google/zoombini/memory.c
M src/mainboard/google/zoombini/romstage.c
M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/zoombini/variants/meowth/memory.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
R src/soc/intel/cannonlake/cnl_memcfg_init.c
R src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
9 files changed, 35 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28248/1
diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index d28f662..656d8b0 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -12,7 +12,7 @@
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CANNONLAKE
- select SOC_INTEL_CANNONLAKE_LPDDR4_INIT
+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c
index e1f5255..e8dae5a 100644
--- a/src/mainboard/google/zoombini/memory.c
+++ b/src/mainboard/google/zoombini/memory.c
@@ -17,9 +17,9 @@
#include <baseboard/gpio.h>
#include <compiler.h>
#include <gpio.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
-static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
+static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {
.dq_map[LP4_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
@@ -82,7 +82,7 @@
.ect = 0,
};
-const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
+const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)
{
return &baseboard_lpddr4_cfg;
}
diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c
index 8e19177..4bd0ede 100644
--- a/src/mainboard/google/zoombini/romstage.c
+++ b/src/mainboard/google/zoombini/romstage.c
@@ -14,7 +14,7 @@
*/
#include <baseboard/variants.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
@@ -24,6 +24,6 @@
.spd_spec.spd_index = variant_memory_sku(),
};
- cannonlake_lpddr4_init(&memupd->FspmConfig,
+ cannonlake_memcfg_init(&memupd->FspmConfig,
variant_lpddr4_config(), &spd);
}
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
index eab081d..eac0fee 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
@@ -17,7 +17,7 @@
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
#include <soc/gpio.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -35,7 +35,7 @@
const struct cros_gpio *variant_cros_gpios(size_t *num);
/* Return LPDDR4 configuration structure. */
-const struct lpddr4_cfg *variant_lpddr4_config(void);
+const struct cnl_mb_cfg *variant_lpddr4_config(void);
/* Return memory SKU for the board. */
size_t variant_memory_sku(void);
diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c
index c72ffea..d672521 100644
--- a/src/mainboard/google/zoombini/variants/meowth/memory.c
+++ b/src/mainboard/google/zoombini/variants/meowth/memory.c
@@ -16,9 +16,9 @@
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
-static const struct lpddr4_cfg meowth_lpddr4_cfg = {
+static const struct cnl_mb_cfg meowth_lpddr4_cfg = {
.dq_map[LP4_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
@@ -86,7 +86,7 @@
.ect = 1,
};
-const struct lpddr4_cfg *variant_lpddr4_config(void)
+const struct cnl_mb_cfg *variant_lpddr4_config(void)
{
return &meowth_lpddr4_cfg;
}
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index e6a2062..ef39706 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -184,7 +184,7 @@
int
default 100
-config SOC_INTEL_CANNONLAKE_LPDDR4_INIT
+config SOC_INTEL_CANNONLAKE_MEMCFG_INIT
bool
default n
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 013e86a..065d92b 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -22,7 +22,7 @@
bootblock-y += p2sb.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
-romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
+romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c
diff --git a/src/soc/intel/cannonlake/cnl_lpddr4_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c
similarity index 79%
rename from src/soc/intel/cannonlake/cnl_lpddr4_init.c
rename to src/soc/intel/cannonlake/cnl_memcfg_init.c
index ea8c410..b4353e3 100644
--- a/src/soc/intel/cannonlake/cnl_lpddr4_init.c
+++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c
@@ -15,12 +15,12 @@
#include <assert.h>
#include <console/console.h>
#include <fsp/util.h>
-#include <soc/cnl_lpddr4_init.h>
+#include <soc/cnl_memcfg_init.h>
#include <spd_bin.h>
#include <string.h>
-static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
- const struct lpddr4_cfg *board_cfg,
+static void meminit_memcfg(FSP_M_CONFIG *mem_cfg,
+ const struct cnl_mb_cfg *board_cfg,
size_t spd_data_len, uintptr_t spd_data_ptr)
{
/*
@@ -58,12 +58,12 @@
/*
* Initialize default LPDDR4 settings using spd data contained in a buffer.
*/
-static void meminit_lpddr4_spd_data(FSP_M_CONFIG *mem_cfg,
- const struct lpddr4_cfg *cnl_cfg,
+static void meminit_spd_data(FSP_M_CONFIG *mem_cfg,
+ const struct cnl_mb_cfg *cnl_cfg,
size_t spd_data_len, uintptr_t spd_data_ptr)
{
assert(spd_data_ptr && spd_data_len);
- meminit_lpddr4(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
+ meminit_memcfg(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
}
/*
@@ -71,8 +71,8 @@
* spd_index. The spd_index is an index into the SPD_SOURCES array defined
* in spd/Makefile.inc.
*/
-static void meminit_lpddr4_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
- const struct lpddr4_cfg *cnl_cfg,
+static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
+ const struct cnl_mb_cfg *cnl_cfg,
int spd_index)
{
size_t spd_data_len;
@@ -86,25 +86,23 @@
/* Memory leak is ok since we have memory mapped boot media */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
- meminit_lpddr4_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
+ meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
}
-/* Initialize LPDDR4 settings for CannonLake */
-void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,
- const struct lpddr4_cfg *cnl_cfg,
+/* Initialize onboard memory configurations for CannonLake */
+void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+ const struct cnl_mb_cfg *cnl_cfg,
const struct spd_info *spd)
{
/* Early Command Training Enabled */
mem_cfg->ECT = cnl_cfg->ect;
mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved;
- mem_cfg->RefClk = 0; /* Auto Select CLK freq */
- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
if (spd->spd_by_index) {
- meminit_lpddr4_cbfs_spd_index(mem_cfg, cnl_cfg,
+ meminit_cbfs_spd_index(mem_cfg, cnl_cfg,
spd->spd_spec.spd_index);
} else {
- meminit_lpddr4_spd_data(mem_cfg, cnl_cfg,
+ meminit_spd_data(mem_cfg, cnl_cfg,
spd->spd_spec.spd_data_ptr_info.spd_data_len,
spd->spd_spec.spd_data_ptr_info.spd_data_ptr);
}
diff --git a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
similarity index 88%
rename from src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h
rename to src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
index db1c3a5..eed714d 100644
--- a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h
+++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_CANNONLAKE_LPDDR4_INIT_H_
-#define _SOC_CANNONLAKE_LPDDR4_INIT_H_
+#ifndef _SOC_CANNONLAKE_MEMCFG_INIT_H_
+#define _SOC_CANNONLAKE_MEMCFG_INIT_H_
#include <stddef.h>
#include <stdint.h>
@@ -24,7 +24,7 @@
#define DQ_BITS_PER_DQS 8
/*
- * Number of LPDDR4 packages, where a "package" represents a 64-bit solution.
+ * Number of memory packages, where a "package" represents a 64-bit solution.
*/
#define LP4_NUM_PACKAGES 2
@@ -49,7 +49,7 @@
};
/* Board-specific lpddr4 dq mapping information */
-struct lpddr4_cfg {
+struct cnl_mb_cfg {
/*
* For each channel, there are 3 sets of DQ byte mappings,
* where each set has a package 0 and a package 1 value (package 0
@@ -97,10 +97,10 @@
};
/*
- * Initialize default LPDDR4 settings for CannonLake.
+ * Initialize default memory configurations for CannonLake.
*/
-void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,
- const struct lpddr4_cfg *cnl_cfg,
+void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+ const struct cnl_mb_cfg *cnl_cfg,
const struct spd_info *spd);
-#endif /* _SOC_CANNONLAKE_LPDDR4_INIT_H_ */
+#endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Gerrit-Change-Number: 28248
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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