<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28248">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Change LPDDR4 to MEMCFG<br><br>Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to<br>make the infrasturture to handle both LPDDR4 and DDR4 cases in the<br>future.<br><br>BUG=N/A<br>TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"<br>compiles successfully.<br><br>Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/google/zoombini/Kconfig<br>M src/mainboard/google/zoombini/memory.c<br>M src/mainboard/google/zoombini/romstage.c<br>M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h<br>M src/mainboard/google/zoombini/variants/meowth/memory.c<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>R src/soc/intel/cannonlake/cnl_memcfg_init.c<br>R src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h<br>9 files changed, 35 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28248/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig</span><br><span>index d28f662..656d8b0 100644</span><br><span>--- a/src/mainboard/google/zoombini/Kconfig</span><br><span>+++ b/src/mainboard/google/zoombini/Kconfig</span><br><span>@@ -12,7 +12,7 @@</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span> select SOC_INTEL_CANNONLAKE</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_CANNONLAKE_LPDDR4_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span> </span><br><span> if BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span> </span><br><span>diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c</span><br><span>index e1f5255..e8dae5a 100644</span><br><span>--- a/src/mainboard/google/zoombini/memory.c</span><br><span>+++ b/src/mainboard/google/zoombini/memory.c</span><br><span>@@ -17,9 +17,9 @@</span><br><span> #include <baseboard/gpio.h></span><br><span> #include <compiler.h></span><br><span> #include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_lpddr4_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct lpddr4_cfg baseboard_lpddr4_cfg = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {</span><br><span> .dq_map[LP4_CH0] = {</span><br><span> /*</span><br><span> * CLK0 goes to package 0 - Bytes[3:0],</span><br><span>@@ -82,7 +82,7 @@</span><br><span> .ect = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct lpddr4_cfg *__weak variant_lpddr4_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)</span><br><span> {</span><br><span> return &baseboard_lpddr4_cfg;</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c</span><br><span>index 8e19177..4bd0ede 100644</span><br><span>--- a/src/mainboard/google/zoombini/romstage.c</span><br><span>+++ b/src/mainboard/google/zoombini/romstage.c</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_lpddr4_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> #include <soc/romstage.h></span><br><span> </span><br><span> void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span>@@ -24,6 +24,6 @@</span><br><span> .spd_spec.spd_index = variant_memory_sku(),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- cannonlake_lpddr4_init(&memupd->FspmConfig,</span><br><span style="color: hsl(120, 100%, 40%);">+ cannonlake_memcfg_init(&memupd->FspmConfig,</span><br><span> variant_lpddr4_config(), &spd);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h</span><br><span>index eab081d..eac0fee 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #ifndef __BASEBOARD_VARIANTS_H__</span><br><span> #define __BASEBOARD_VARIANTS_H__</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_lpddr4_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <stdint.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -35,7 +35,7 @@</span><br><span> const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span> </span><br><span> /* Return LPDDR4 configuration structure. */</span><br><span style="color: hsl(0, 100%, 40%);">-const struct lpddr4_cfg *variant_lpddr4_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cnl_mb_cfg *variant_lpddr4_config(void);</span><br><span> </span><br><span> /* Return memory SKU for the board. */</span><br><span> size_t variant_memory_sku(void);</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c</span><br><span>index c72ffea..d672521 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/memory.c</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/memory.c</span><br><span>@@ -16,9 +16,9 @@</span><br><span> #include <baseboard/variants.h></span><br><span> #include <baseboard/gpio.h></span><br><span> #include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_lpddr4_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct lpddr4_cfg meowth_lpddr4_cfg = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cnl_mb_cfg meowth_lpddr4_cfg = {</span><br><span> .dq_map[LP4_CH0] = {</span><br><span> /*</span><br><span> * CLK0 goes to package 0 - Bytes[3:0],</span><br><span>@@ -86,7 +86,7 @@</span><br><span> .ect = 1,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct lpddr4_cfg *variant_lpddr4_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cnl_mb_cfg *variant_lpddr4_config(void)</span><br><span> {</span><br><span> return &meowth_lpddr4_cfg;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index e6a2062..ef39706 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -184,7 +184,7 @@</span><br><span> int</span><br><span> default 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config SOC_INTEL_CANNONLAKE_LPDDR4_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span> bool</span><br><span> default n</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 013e86a..065d92b 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -22,7 +22,7 @@</span><br><span> bootblock-y += p2sb.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += gspi.c</span><br><span> romstage-y += i2c.c</span><br><span>diff --git a/src/soc/intel/cannonlake/cnl_lpddr4_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c</span><br><span>similarity index 79%</span><br><span>rename from src/soc/intel/cannonlake/cnl_lpddr4_init.c</span><br><span>rename to src/soc/intel/cannonlake/cnl_memcfg_init.c</span><br><span>index ea8c410..b4353e3 100644</span><br><span>--- a/src/soc/intel/cannonlake/cnl_lpddr4_init.c</span><br><span>+++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c</span><br><span>@@ -15,12 +15,12 @@</span><br><span> #include <assert.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_lpddr4_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> #include <spd_bin.h></span><br><span> #include <string.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(0, 100%, 40%);">- const struct lpddr4_cfg *board_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+static void meminit_memcfg(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cnl_mb_cfg *board_cfg,</span><br><span> size_t spd_data_len, uintptr_t spd_data_ptr)</span><br><span> {</span><br><span> /*</span><br><span>@@ -58,12 +58,12 @@</span><br><span> /*</span><br><span> * Initialize default LPDDR4 settings using spd data contained in a buffer.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void meminit_lpddr4_spd_data(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(0, 100%, 40%);">- const struct lpddr4_cfg *cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+static void meminit_spd_data(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cnl_mb_cfg *cnl_cfg,</span><br><span> size_t spd_data_len, uintptr_t spd_data_ptr)</span><br><span> {</span><br><span> assert(spd_data_ptr && spd_data_len);</span><br><span style="color: hsl(0, 100%, 40%);">- meminit_lpddr4(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+ meminit_memcfg(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>@@ -71,8 +71,8 @@</span><br><span> * spd_index. The spd_index is an index into the SPD_SOURCES array defined</span><br><span> * in spd/Makefile.inc.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void meminit_lpddr4_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(0, 100%, 40%);">- const struct lpddr4_cfg *cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cnl_mb_cfg *cnl_cfg,</span><br><span> int spd_index)</span><br><span> {</span><br><span> size_t spd_data_len;</span><br><span>@@ -86,25 +86,23 @@</span><br><span> /* Memory leak is ok since we have memory mapped boot media */</span><br><span> assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));</span><br><span> spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span style="color: hsl(0, 100%, 40%);">- meminit_lpddr4_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+ meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Initialize LPDDR4 settings for CannonLake */</span><br><span style="color: hsl(0, 100%, 40%);">-void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(0, 100%, 40%);">- const struct lpddr4_cfg *cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+/* Initialize onboard memory configurations for CannonLake */</span><br><span style="color: hsl(120, 100%, 40%);">+void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cnl_mb_cfg *cnl_cfg,</span><br><span> const struct spd_info *spd)</span><br><span> {</span><br><span> /* Early Command Training Enabled */</span><br><span> mem_cfg->ECT = cnl_cfg->ect;</span><br><span> mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span> </span><br><span> if (spd->spd_by_index) {</span><br><span style="color: hsl(0, 100%, 40%);">- meminit_lpddr4_cbfs_spd_index(mem_cfg, cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ meminit_cbfs_spd_index(mem_cfg, cnl_cfg,</span><br><span> spd->spd_spec.spd_index);</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- meminit_lpddr4_spd_data(mem_cfg, cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ meminit_spd_data(mem_cfg, cnl_cfg,</span><br><span> spd->spd_spec.spd_data_ptr_info.spd_data_len,</span><br><span> spd->spd_spec.spd_data_ptr_info.spd_data_ptr);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h</span><br><span>similarity index 88%</span><br><span>rename from src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h</span><br><span>rename to src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h</span><br><span>index db1c3a5..eed714d 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h</span><br><span>@@ -13,8 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _SOC_CANNONLAKE_LPDDR4_INIT_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _SOC_CANNONLAKE_LPDDR4_INIT_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_CANNONLAKE_MEMCFG_INIT_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_CANNONLAKE_MEMCFG_INIT_H_</span><br><span> </span><br><span> #include <stddef.h></span><br><span> #include <stdint.h></span><br><span>@@ -24,7 +24,7 @@</span><br><span> #define DQ_BITS_PER_DQS 8</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Number of LPDDR4 packages, where a "package" represents a 64-bit solution.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Number of memory packages, where a "package" represents a 64-bit solution.</span><br><span> */</span><br><span> #define LP4_NUM_PACKAGES 2</span><br><span> </span><br><span>@@ -49,7 +49,7 @@</span><br><span> };</span><br><span> </span><br><span> /* Board-specific lpddr4 dq mapping information */</span><br><span style="color: hsl(0, 100%, 40%);">-struct lpddr4_cfg {</span><br><span style="color: hsl(120, 100%, 40%);">+struct cnl_mb_cfg {</span><br><span> /*</span><br><span> * For each channel, there are 3 sets of DQ byte mappings,</span><br><span> * where each set has a package 0 and a package 1 value (package 0</span><br><span>@@ -97,10 +97,10 @@</span><br><span> };</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Initialize default LPDDR4 settings for CannonLake.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Initialize default memory configurations for CannonLake.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(0, 100%, 40%);">- const struct lpddr4_cfg *cnl_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cnl_mb_cfg *cnl_cfg,</span><br><span> const struct spd_info *spd);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _SOC_CANNONLAKE_LPDDR4_INIT_H_ */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28248">change 28248</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28248"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 </div>
<div style="display:none"> Gerrit-Change-Number: 28248 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>