[coreboot-gerrit] Change in coreboot[master]: Kconfig, Makefile.inc: Remove all traces of ifdfake
Angel Pons (Code Review)
gerrit at coreboot.org
Mon Aug 20 16:42:17 CEST 2018
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28233
Change subject: Kconfig, Makefile.inc: Remove all traces of ifdfake
......................................................................
Kconfig, Makefile.inc: Remove all traces of ifdfake
Since ifdfake has been deprecated in favor of better alternatives, there
is no need to support it any further. Remove it from the build system.
Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2
Signed-off-by: Angel Pons <th3fanbus at gmail.com>
---
M Makefile.inc
M src/southbridge/intel/common/firmware/Kconfig
M src/southbridge/intel/common/firmware/Makefile.inc
3 files changed, 4 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28233/1
diff --git a/Makefile.inc b/Makefile.inc
index 7ce2360..46e833e 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -457,7 +457,7 @@
endif
additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \
- $(objutil)/ifdfake $(objutil)/options $(objutil)/amdfwtool \
+ $(objutil)/options $(objutil)/amdfwtool \
$(objutil)/cbootimage $(objutil)/bimgtool
export $(COREBOOT_EXPORTS)
@@ -519,11 +519,6 @@
+$(MAKE) -C $(top)/util/ifdtool
cp -a $(top)/util/ifdtool/ifdtool $@
-IFDFAKE:=$(objutil)/ifdfake/ifdfake
-$(IFDFAKE): $(top)/util/ifdfake/ifdfake.c
- @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
- $(HOSTCC) $(HOSTCFLAGS) -o $@ $<
-
AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c
@printf " HOSTCC $(subst $(obj)/,,$(@))\n"
@@ -603,7 +598,7 @@
include util/crossgcc/Makefile.inc
.PHONY: tools
-tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)
+tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)
###########################################################################
# Common recipes for all stages
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index c9cf6f8..590d120 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -33,7 +33,7 @@
config IFD_BIN_PATH
string "Path and filename of the descriptor.bin file"
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
- depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
+ depends on HAVE_IFD_BIN
config HAVE_ME_BIN
bool "Add Intel ME/TXE firmware"
@@ -132,67 +132,6 @@
depends on HAVE_EC_BIN
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin"
-##### Fake IFD #####
-
-config BUILD_WITH_FAKE_IFD
- bool "Build with a fake IFD" if !HAVE_IFD_BIN
- help
- If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
- board, you can select this option and coreboot will build without it.
- The resulting coreboot.rom will not contain all parts required
- to get coreboot running on your board. You can however write only the
- BIOS section to your board's flash ROM and keep the other sections
- untouched. Unfortunately the current version of flashrom doesn't
- support this yet. But there is a patch pending [1].
-
- WARNING: Never write a complete coreboot.rom to your flash ROM if it
- was built with a fake IFD. It just won't work.
-
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
- depends on BUILD_WITH_FAKE_IFD
- string "BIOS Region Starting:Ending addresses within the ROM"
- default ""
- help
- The BIOS region is typically the size of the CBFS area, and is located
- at the end of the ROM space.
-
- For an 8MB ROM with a 3MB CBFS area, this would look like:
- 0x00500000:0x007fffff
-
-config IFD_ME_SECTION
- depends on BUILD_WITH_FAKE_IFD
- string "ME/TXE Region Starting:Ending addresses within the ROM"
- default ""
- help
- The ME/TXE region typically starts at around 0x1000 and often fills the
- ROM space not used by CBFS.
-
- For an 8MB ROM with a 3MB CBFS area, this might look like:
- 0x00001000:0x004fffff
-
-config IFD_GBE_SECTION
- depends on BUILD_WITH_FAKE_IFD
- string "GBE Region Starting:Ending addresses within the ROM"
- default ""
- help
- The Gigabit Ethernet ROM region is used when an Intel NIC is built into
- the Southbridge/SOC and the platform uses this device instead of an external
- PCIe NIC. It will be located between the ME/TXE and the BIOS region.
-
- Leave this empty if you're unsure.
-
-config IFD_PLATFORM_SECTION
- depends on BUILD_WITH_FAKE_IFD
- string "Platform Region Starting:Ending addresses within the Rom"
- default ""
- help
- The Platform region is used for platform specific data.
- It will be located between the ME/TXE and the BIOS region.
-
- Leave this empty if you're unsure.
-
config LOCK_MANAGEMENT_ENGINE
bool "Lock ME/TXE section"
default n
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
index 737a79d..a1c09c9 100644
--- a/src/southbridge/intel/common/firmware/Makefile.inc
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -24,29 +24,12 @@
INTERMEDIATE+=add_intel_firmware
endif
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-INTERMEDIATE+=add_intel_firmware
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
- $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
- $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
- $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),)
IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET)
endif
-endif
-add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
- printf "\n** WARNING **\n"
- printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
- printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
- printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
- printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
- $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
+add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL)
printf " DD Adding Intel Firmware Descriptor\n"
dd if=$(IFD_BIN_PATH) \
of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
@@ -88,11 +71,6 @@
$(objutil)/ifdtool/ifdtool \
$(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
- printf " IFDTOOL Unlocking Management Engine\n"
- $(objutil)/ifdtool/ifdtool \
- $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre
- mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
endif
ifeq ($(CONFIG_EM100),y)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2
Gerrit-Change-Number: 28233
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus at gmail.com>
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