<p>Angel Pons has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28233">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Kconfig, Makefile.inc: Remove all traces of ifdfake<br><br>Since ifdfake has been deprecated in favor of better alternatives, there<br>is no need to support it any further. Remove it from the build system.<br><br>Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2<br>Signed-off-by: Angel Pons <th3fanbus@gmail.com><br>---<br>M Makefile.inc<br>M src/southbridge/intel/common/firmware/Kconfig<br>M src/southbridge/intel/common/firmware/Makefile.inc<br>3 files changed, 4 insertions(+), 92 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28233/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Makefile.inc b/Makefile.inc</span><br><span>index 7ce2360..46e833e 100644</span><br><span>--- a/Makefile.inc</span><br><span>+++ b/Makefile.inc</span><br><span>@@ -457,7 +457,7 @@</span><br><span> endif</span><br><span> </span><br><span> additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \</span><br><span style="color: hsl(0, 100%, 40%);">- $(objutil)/ifdfake $(objutil)/options $(objutil)/amdfwtool \</span><br><span style="color: hsl(120, 100%, 40%);">+ $(objutil)/options $(objutil)/amdfwtool \</span><br><span> $(objutil)/cbootimage $(objutil)/bimgtool</span><br><span> </span><br><span> export $(COREBOOT_EXPORTS)</span><br><span>@@ -519,11 +519,6 @@</span><br><span> +$(MAKE) -C $(top)/util/ifdtool</span><br><span> cp -a $(top)/util/ifdtool/ifdtool $@</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-IFDFAKE:=$(objutil)/ifdfake/ifdfake</span><br><span style="color: hsl(0, 100%, 40%);">-$(IFDFAKE): $(top)/util/ifdfake/ifdfake.c</span><br><span style="color: hsl(0, 100%, 40%);">- @printf " HOSTCC $(subst $(obj)/,,$(@))\n"</span><br><span style="color: hsl(0, 100%, 40%);">- $(HOSTCC) $(HOSTCFLAGS) -o $@ $<</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool</span><br><span> $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c</span><br><span> @printf " HOSTCC $(subst $(obj)/,,$(@))\n"</span><br><span>@@ -603,7 +598,7 @@</span><br><span> include util/crossgcc/Makefile.inc</span><br><span> </span><br><span> .PHONY: tools</span><br><span style="color: hsl(0, 100%, 40%);">-tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)</span><br><span style="color: hsl(120, 100%, 40%);">+tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)</span><br><span> </span><br><span> ###########################################################################</span><br><span> # Common recipes for all stages</span><br><span>diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig</span><br><span>index c9cf6f8..590d120 100644</span><br><span>--- a/src/southbridge/intel/common/firmware/Kconfig</span><br><span>+++ b/src/southbridge/intel/common/firmware/Kconfig</span><br><span>@@ -33,7 +33,7 @@</span><br><span> config IFD_BIN_PATH</span><br><span> string "Path and filename of the descriptor.bin file"</span><br><span> default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"</span><br><span style="color: hsl(0, 100%, 40%);">- depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on HAVE_IFD_BIN</span><br><span> </span><br><span> config HAVE_ME_BIN</span><br><span> bool "Add Intel ME/TXE firmware"</span><br><span>@@ -132,67 +132,6 @@</span><br><span> depends on HAVE_EC_BIN</span><br><span> default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-##### Fake IFD #####</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Build with a fake IFD" if !HAVE_IFD_BIN</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- If you don't have an Intel Firmware Descriptor (descriptor.bin) for your</span><br><span style="color: hsl(0, 100%, 40%);">- board, you can select this option and coreboot will build without it.</span><br><span style="color: hsl(0, 100%, 40%);">- The resulting coreboot.rom will not contain all parts required</span><br><span style="color: hsl(0, 100%, 40%);">- to get coreboot running on your board. You can however write only the</span><br><span style="color: hsl(0, 100%, 40%);">- BIOS section to your board's flash ROM and keep the other sections</span><br><span style="color: hsl(0, 100%, 40%);">- untouched. Unfortunately the current version of flashrom doesn't</span><br><span style="color: hsl(0, 100%, 40%);">- support this yet. But there is a patch pending [1].</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- WARNING: Never write a complete coreboot.rom to your flash ROM if it</span><br><span style="color: hsl(0, 100%, 40%);">- was built with a fake IFD. It just won't work.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IFD_BIOS_SECTION</span><br><span style="color: hsl(0, 100%, 40%);">- depends on BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(0, 100%, 40%);">- string "BIOS Region Starting:Ending addresses within the ROM"</span><br><span style="color: hsl(0, 100%, 40%);">- default ""</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- The BIOS region is typically the size of the CBFS area, and is located</span><br><span style="color: hsl(0, 100%, 40%);">- at the end of the ROM space.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- For an 8MB ROM with a 3MB CBFS area, this would look like:</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00500000:0x007fffff</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IFD_ME_SECTION</span><br><span style="color: hsl(0, 100%, 40%);">- depends on BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(0, 100%, 40%);">- string "ME/TXE Region Starting:Ending addresses within the ROM"</span><br><span style="color: hsl(0, 100%, 40%);">- default ""</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- The ME/TXE region typically starts at around 0x1000 and often fills the</span><br><span style="color: hsl(0, 100%, 40%);">- ROM space not used by CBFS.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- For an 8MB ROM with a 3MB CBFS area, this might look like:</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00001000:0x004fffff</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IFD_GBE_SECTION</span><br><span style="color: hsl(0, 100%, 40%);">- depends on BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(0, 100%, 40%);">- string "GBE Region Starting:Ending addresses within the ROM"</span><br><span style="color: hsl(0, 100%, 40%);">- default ""</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- The Gigabit Ethernet ROM region is used when an Intel NIC is built into</span><br><span style="color: hsl(0, 100%, 40%);">- the Southbridge/SOC and the platform uses this device instead of an external</span><br><span style="color: hsl(0, 100%, 40%);">- PCIe NIC. It will be located between the ME/TXE and the BIOS region.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Leave this empty if you're unsure.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IFD_PLATFORM_SECTION</span><br><span style="color: hsl(0, 100%, 40%);">- depends on BUILD_WITH_FAKE_IFD</span><br><span style="color: hsl(0, 100%, 40%);">- string "Platform Region Starting:Ending addresses within the Rom"</span><br><span style="color: hsl(0, 100%, 40%);">- default ""</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- The Platform region is used for platform specific data.</span><br><span style="color: hsl(0, 100%, 40%);">- It will be located between the ME/TXE and the BIOS region.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Leave this empty if you're unsure.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config LOCK_MANAGEMENT_ENGINE</span><br><span> bool "Lock ME/TXE section"</span><br><span> default n</span><br><span>diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc</span><br><span>index 737a79d..a1c09c9 100644</span><br><span>--- a/src/southbridge/intel/common/firmware/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/common/firmware/Makefile.inc</span><br><span>@@ -24,29 +24,12 @@</span><br><span> INTERMEDIATE+=add_intel_firmware</span><br><span> endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)</span><br><span style="color: hsl(0, 100%, 40%);">-INTERMEDIATE+=add_intel_firmware</span><br><span style="color: hsl(0, 100%, 40%);">-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin</span><br><span style="color: hsl(0, 100%, 40%);">-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \</span><br><span style="color: hsl(0, 100%, 40%);">- $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \</span><br><span style="color: hsl(0, 100%, 40%);">- $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \</span><br><span style="color: hsl(0, 100%, 40%);">- $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)</span><br><span> ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),)</span><br><span> IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET)</span><br><span> endif</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)</span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)</span><br><span style="color: hsl(0, 100%, 40%);">- printf "\n** WARNING **\n"</span><br><span style="color: hsl(0, 100%, 40%);">- printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"</span><br><span style="color: hsl(0, 100%, 40%);">- printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"</span><br><span style="color: hsl(0, 100%, 40%);">- printf "flash ROM! Make sure that you only write valid flash regions.\n\n"</span><br><span style="color: hsl(0, 100%, 40%);">- printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"</span><br><span style="color: hsl(0, 100%, 40%);">- $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(120, 100%, 40%);">+add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL)</span><br><span> printf " DD Adding Intel Firmware Descriptor\n"</span><br><span> dd if=$(IFD_BIN_PATH) \</span><br><span> of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1</span><br><span>@@ -88,11 +71,6 @@</span><br><span> $(objutil)/ifdtool/ifdtool \</span><br><span> $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre</span><br><span> mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre</span><br><span style="color: hsl(0, 100%, 40%);">-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)</span><br><span style="color: hsl(0, 100%, 40%);">- printf " IFDTOOL Unlocking Management Engine\n"</span><br><span style="color: hsl(0, 100%, 40%);">- $(objutil)/ifdtool/ifdtool \</span><br><span style="color: hsl(0, 100%, 40%);">- $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre</span><br><span style="color: hsl(0, 100%, 40%);">- mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre</span><br><span> endif</span><br><span> </span><br><span> ifeq ($(CONFIG_EM100),y)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28233">change 28233</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28233"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 </div>
<div style="display:none"> Gerrit-Change-Number: 28233 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> </div>