[coreboot-gerrit] Change in coreboot[master]: Fix PCI ACPI _OSC methods
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Aug 17 23:09:20 CEST 2018
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28121 )
Change subject: Fix PCI ACPI _OSC methods
......................................................................
Fix PCI ACPI _OSC methods
Fix the IASL build warnings:
Object is not referenced (Name [CDW2] is within a method [_OSC])
Object is not referenced (Name [CDW3] is within a method [_OSC])
Remove the not referenced objects. They are not needed.
BUG=b:112476331
TEST=IASL doesn't give the warning.
Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Signed-off-by: Marc Jones <marcj303 at gmail.com>
Reviewed-on: https://review.coreboot.org/28121
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/northbridge/intel/i945/acpi/i945.asl
M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/cimx/sb800/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
5 files changed, 5 insertions(+), 25 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 5a93238..79fb371 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -20,17 +20,13 @@
/* Operating System Capabilities Method */
Method (_OSC, 4)
{
- // Create DWord-addressable fields from the Capabilities Buffer
- CreateDWordField(Arg3, 0, CDW1)
- CreateDWordField(Arg3, 4, CDW2)
- CreateDWordField(Arg3, 8, CDW3)
-
/* Check for proper PCI/PCIe UUID */
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return(Arg3)
} Else {
+ CreateDWordField(Arg3, 0, CDW1)
Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1
Return(Arg3)
}
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 2855b23..cdda503 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -22,17 +22,13 @@
/* Operating System Capabilities Method */
Method(_OSC,4)
{
- // Create DWord-addressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
/* Check for proper PCI/PCIe UUID */
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
} Else {
+ CreateDWordField(Arg3,0,CDW1)
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
index efd6a93..2bbaa25 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
@@ -20,17 +20,13 @@
/* Operating System Capabilities Method */
Method(_OSC,4)
{
- // Create DWord-addressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
/* Check for proper PCI/PCIe UUID */
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
} Else {
+ CreateDWordField(Arg3,0,CDW1)
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 6f0826f..2dc3438 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -19,17 +19,13 @@
/* Operating System Capabilities Method */
Method(_OSC,4)
{
- // Create DWord-addressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
/* Check for proper PCI/PCIe UUID */
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
} Else {
+ CreateDWordField(Arg3,0,CDW1)
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 2586dd4..b33a440 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -20,17 +20,13 @@
/* Operating System Capabilities Method */
Method(_OSC,4)
{
- // Create DWord-addressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
/* Check for proper PCI/PCIe UUID */
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
} Else {
+ CreateDWordField(Arg3,0,CDW1)
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Gerrit-Change-Number: 28121
Gerrit-PatchSet: 2
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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