[coreboot-gerrit] Change in coreboot[master]: arm64: Factor our common parts of romstage execution flow
Julius Werner (Code Review)
gerrit at coreboot.org
Fri Aug 17 20:47:41 CEST 2018
Julius Werner has uploaded this change for review. ( https://review.coreboot.org/28199
Change subject: arm64: Factor our common parts of romstage execution flow
......................................................................
arm64: Factor our common parts of romstage execution flow
The romstage main() entry point on arm64 boards is usually in mainboard
code, but there are a handful of lines that are always needed in there
and not really mainboard specific (or chipset specific). We keep arguing
every once in a while that this isn't ideal, so rather than arguing any
longer let's just fix it. This patch moves the main() function into arch
code with callbacks that the platform can hook into. (This approach can
probably be expanded onto other architectures, so when that happens this
file should move into src/lib.)
Tested on Cheza and Kevin. I think the approach is straight-forward
enough that we can take this without testing every board. (Note that in
a few cases, this delays some platform-specific calls until after
console_init() and exception_init()... since these functions don't
really take that long, especially if there is no serial console
configured, I don't expect this to cause any issues.)
Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/arch/arm64/Makefile.inc
M src/arch/arm64/include/arch/stages.h
A src/arch/arm64/romstage.c
M src/mainboard/cavium/cn8100_sff_evb/romstage.c
M src/mainboard/google/cheza/romstage.c
M src/mainboard/google/gru/romstage.c
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/oak/romstage.c
8 files changed, 59 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28199/1
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index e2c44eb4..6bb7196 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -107,6 +107,7 @@
romstage-y += memset.S
romstage-y += memcpy.S
romstage-y += memmove.S
+romstage-y += romstage.c
romstage-y += transition.c transition_asm.S
rmodules_arm64-y += memset.S
diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h
index 9a88ea7..2d6d583 100644
--- a/src/arch/arm64/include/arch/stages.h
+++ b/src/arch/arm64/include/arch/stages.h
@@ -21,4 +21,11 @@
void stage_entry(void);
+/* This function is the romstage platform entry point, and should contain all
+ chipset and mainboard setup until DRAM is initialized and accessible. */
+void platform_romstage_main(void);
+/* This is an optional hook to run further chipset or mainboard code after DRAM
+ and associated support frameworks (like CBMEM) have been initialized. */
+void platform_romstage_postram(void);
+
#endif
diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c
new file mode 100644
index 0000000..8cdb16b
--- /dev/null
+++ b/src/arch/arm64/romstage.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <timestamp.h>
+
+__weak void platform_romstage_main(void) { /* no-op, for bring-up */ }
+__weak void platform_romstage_postram(void) { /* no-op */ }
+
+void main(void)
+{
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ console_init();
+ exception_init();
+
+ platform_romstage_main();
+ cbmem_initialize_empty();
+ platform_romstage_postram();
+
+ run_ramstage();
+}
diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
index e8e5cd6..7bb53e3 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
@@ -14,34 +14,24 @@
*
*/
-#include <arch/exception.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
+#include <arch/stages.h>
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
#include <stdlib.h>
-#include <console/console.h>
-#include <program_loading.h>
#include <libbdk-hal/bdk-config.h>
#include <string.h>
extern const struct bdk_devicetree_key_value devtree[];
-void main(void)
+void platform_romstage_main(void)
{
watchdog_poke(0);
- console_init();
- exception_init();
-
bdk_config_set_fdt(devtree);
sdram_init();
soc_mmu_init();
watchdog_poke(0);
-
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c
index c930016..ad85061 100644
--- a/src/mainboard/google/cheza/romstage.c
+++ b/src/mainboard/google/cheza/romstage.c
@@ -13,17 +13,8 @@
* GNU General Public License for more details.
*/
-#include <arch/exception.h>
-#include <cbmem.h>
-#include <halt.h>
-#include <program_loading.h>
-#include <console/console.h>
-#include <timestamp.h>
+#include <arch/stages.h>
-void main(void)
+void platform_romstage_main(void)
{
- console_init();
- exception_init();
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 9f938f3..edf440d 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -14,24 +14,14 @@
*
*/
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/exception.h>
#include <arch/mmu.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <gpio.h>
-#include <console/console.h>
+#include <arch/stages.h>
#include <delay.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-#include <soc/addressmap.h>
#include <soc/mmu_operations.h>
#include <soc/tsadc.h>
#include <soc/sdram.h>
#include <symbols.h>
#include <soc/usb.h>
-#include <stdlib.h>
#include "board.h"
#include "pwm_regulator.h"
@@ -70,11 +60,9 @@
reset_usb_otg1();
}
-void main(void)
+void platform_romstage_main(void)
{
- console_init();
tsadc_init(TSHUT_POL_HIGH);
- exception_init();
/* Init DVS to conservative values. */
init_dvs_outputs();
@@ -87,6 +75,4 @@
mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB,
CACHED_MEM);
mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 342a0ba..9eeaa68 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -13,21 +13,10 @@
* GNU General Public License for more details.
*/
-#include <arch/exception.h>
-#include <console/console.h>
-#include <program_loading.h>
+#include <arch/stages.h>
#include <soc/mmu_operations.h>
-#include <timestamp.h>
-void main(void)
+void platform_romstage_main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- /* Init UART baudrate when PLL on. */
- console_init();
- exception_init();
-
mtk_mmu_after_dram();
-
- run_ramstage();
}
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index 9f5ce5f..754c40c 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -12,39 +12,21 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/mmu.h>
-#include <boardid.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-#include <symbols.h>
-#include <timer.h>
-#include <timestamp.h>
+#include <arch/stages.h>
+#include <boardid.h>
#include <soc/emi.h>
#include <soc/mmu_operations.h>
#include <soc/mt6391.h>
#include <soc/pll.h>
#include <soc/rtc.h>
+#include <timer.h>
-void main(void)
+void platform_romstage_main(void)
{
int stabilize_usec;
struct stopwatch sw;
- timestamp_add_now(TS_START_ROMSTAGE);
-
- /* init uart baudrate when pll on */
- console_init();
- exception_init();
-
rtc_boot();
/* Raise CPU voltage to allow higher frequency */
@@ -64,9 +46,4 @@
mt_pll_raise_ca53_freq(1700 * MHz);
mtk_mmu_after_dram();
-
- /* should be called after memory init */
- cbmem_initialize_empty();
-
- run_ramstage();
}
--
To view, visit https://review.coreboot.org/28199
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe
Gerrit-Change-Number: 28199
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180817/61b1b4d6/attachment-0001.html>
More information about the coreboot-gerrit
mailing list