[coreboot-gerrit] Change in coreboot[master]: cbtable: remove chromeos_acpi from cbtable
Joel Kitching (Code Review)
gerrit at coreboot.org
Fri Aug 17 13:08:50 CEST 2018
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28190
Change subject: cbtable: remove chromeos_acpi from cbtable
......................................................................
cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching at google.com>
---
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
M src/soc/amd/stoneyridge/include/soc/nvs.h
M src/soc/intel/apollolake/include/soc/nvs.h
M src/soc/intel/baytrail/include/soc/device_nvs.h
M src/soc/intel/baytrail/include/soc/nvs.h
M src/soc/intel/braswell/include/soc/device_nvs.h
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/broadwell/include/soc/device_nvs.h
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/cannonlake/include/soc/nvs.h
M src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
M src/soc/intel/skylake/include/soc/device_nvs.h
M src/soc/intel/skylake/include/soc/nvs.h
M src/southbridge/intel/bd82x6x/nvs.h
M src/southbridge/intel/fsp_bd82x6x/nvs.h
M src/southbridge/intel/fsp_i89xx/nvs.h
M src/southbridge/intel/ibexpeak/nvs.h
M src/southbridge/intel/lynxpoint/nvs.h
M src/vendorcode/google/chromeos/gnvs.h
23 files changed, 24 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28190/1
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 4cf57c5..1568526 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -200,7 +200,6 @@
struct cb_gpio gpios[0];
};
-#define CB_TAG_CHROMEOS_ACPI 0x0015
#define CB_TAG_VBNV 0x0019
#define CB_TAG_VBOOT_HANDOFF 0x0020
#define CB_TAG_DMA 0x0022
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 66933e3..bd64cdb 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -97,8 +97,6 @@
void *vboot_handoff;
u32 vboot_handoff_size;
- void *chromeos_acpi_addr;
- u32 chromeos_acpi_size;
#if IS_ENABLED(CONFIG_LP_ARCH_X86)
int x86_rom_var_mtrr_index;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index b879987..2189161 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -106,14 +106,6 @@
info->gpios[i] = gpios->gpios[i];
}
-static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct lb_range *chromeos_acpi = (struct lb_range *) ptr;
-
- info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);
- info->chromeos_acpi_size = chromeos_acpi->range_size;
-}
-
static void cb_parse_mac_addresses(unsigned char *ptr,
struct sysinfo_t *info)
{
@@ -357,9 +349,6 @@
case CB_TAG_GPIO:
cb_parse_gpios(ptr, info);
break;
- case CB_TAG_CHROMEOS_ACPI:
- cb_parse_chromeos_acpi(ptr, info);
- break;
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 34726ab..6ca0f77 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -290,7 +290,6 @@
struct lb_gpio gpios[0];
};
-#define LB_TAG_CHROMEOS_ACPI 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6b0e1a0..62b3aaa 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -195,19 +195,6 @@
}
}
-static void lb_chromeos_acpi(struct lb_header *header)
-{
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- struct lb_range *chromeos_acpi;
-
- chromeos_acpi = (struct lb_range *)lb_new_record(header);
- chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
- chromeos_acpi->size = sizeof(*chromeos_acpi);
- acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
- &chromeos_acpi->range_size);
-#endif
-}
-
static void lb_vbnv(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_PC80_SYSTEM)
@@ -547,9 +534,6 @@
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
- /* pass along the chromeos_acpi_t buffer address */
- lb_chromeos_acpi(head);
-
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index b4f7213..bcac3a9 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -55,6 +55,6 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index c7be979..3250aeb 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -53,6 +53,6 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index b4fe65e..bc6f7ec 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 21cdb14..715929d 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -102,7 +102,7 @@
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 268655e..8ed534e 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 89a434b..05831bb 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -106,7 +106,7 @@
/* LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index 15240d1..d17b3d4 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define SIO_NVS_DMA 0
#define SIO_NVS_I2C0 1
#define SIO_NVS_I2C1 2
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 34673d5..2e51e1b 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -94,7 +94,7 @@
/* Device specific (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h
index 6c64f3a..1e55625 100644
--- a/src/soc/intel/cannonlake/include/soc/nvs.h
+++ b/src/soc/intel/cannonlake/include/soc/nvs.h
@@ -46,7 +46,7 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
index 5bafea6..8eff8cd 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h
index 02c9e65..2b7d126 100644
--- a/src/soc/intel/skylake/include/soc/device_nvs.h
+++ b/src/soc/intel/skylake/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define SIO_NVS_I2C0 0
#define SIO_NVS_I2C1 1
#define SIO_NVS_I2C2 2
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index bd3610e..53fdded 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -102,6 +102,6 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 207f763..537139d 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -154,7 +154,7 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h
index a0e063c..c8af5b9 100644
--- a/src/southbridge/intel/fsp_bd82x6x/nvs.h
+++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h
@@ -150,7 +150,7 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h
index a0e063c..c8af5b9 100644
--- a/src/southbridge/intel/fsp_i89xx/nvs.h
+++ b/src/southbridge/intel/fsp_i89xx/nvs.h
@@ -150,7 +150,7 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index 8703911..7b9fd24 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -152,7 +152,7 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index e7d4a8b..fd0d8bc 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -128,7 +128,7 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index e865c0e..62fa08c 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -41,6 +41,18 @@
#define ACTIVE_ECFW_RO 0
#define ACTIVE_ECFW_RW 1
+/*
+ * chromeos_acpi_t portion of ACPI GNVS is assumed to live at
+ * 0x100 - 0x1000. When defining global_nvs_t, use check_member
+ * to ensure that it is properly aligned:
+ *
+ * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+ */
+#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
+
+/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
+#define GNVS_DEVICE_NVS_OFFSET 0x1000
+
typedef struct {
/* ChromeOS specific */
u32 vbt0; // 00 boot reason
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Gerrit-Change-Number: 28190
Gerrit-PatchSet: 1
Gerrit-Owner: Joel Kitching <kitching at google.com>
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