<p>Joel Kitching has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28190">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cbtable: remove chromeos_acpi from cbtable<br><br>Since we can derive chromeos_acpi's location from that of<br>ACPI GNVS, remove chromeos_acpi entry from cbtable and<br>instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.<br><br>BUG=b:112288216<br>TEST=None<br>CQ-DEPEND=CL:1179725<br><br>Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9<br>Signed-off-by: Joel Kitching <kitching@google.com><br>---<br>M payloads/libpayload/include/coreboot_tables.h<br>M payloads/libpayload/include/sysinfo.h<br>M payloads/libpayload/libc/coreboot.c<br>M src/commonlib/include/commonlib/coreboot_tables.h<br>M src/lib/coreboot_table.c<br>M src/soc/amd/stoneyridge/include/soc/nvs.h<br>M src/soc/intel/apollolake/include/soc/nvs.h<br>M src/soc/intel/baytrail/include/soc/device_nvs.h<br>M src/soc/intel/baytrail/include/soc/nvs.h<br>M src/soc/intel/braswell/include/soc/device_nvs.h<br>M src/soc/intel/braswell/include/soc/nvs.h<br>M src/soc/intel/broadwell/include/soc/device_nvs.h<br>M src/soc/intel/broadwell/include/soc/nvs.h<br>M src/soc/intel/cannonlake/include/soc/nvs.h<br>M src/soc/intel/fsp_baytrail/include/soc/device_nvs.h<br>M src/soc/intel/skylake/include/soc/device_nvs.h<br>M src/soc/intel/skylake/include/soc/nvs.h<br>M src/southbridge/intel/bd82x6x/nvs.h<br>M src/southbridge/intel/fsp_bd82x6x/nvs.h<br>M src/southbridge/intel/fsp_i89xx/nvs.h<br>M src/southbridge/intel/ibexpeak/nvs.h<br>M src/southbridge/intel/lynxpoint/nvs.h<br>M src/vendorcode/google/chromeos/gnvs.h<br>23 files changed, 24 insertions(+), 58 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28190/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h</span><br><span>index 4cf57c5..1568526 100644</span><br><span>--- a/payloads/libpayload/include/coreboot_tables.h</span><br><span>+++ b/payloads/libpayload/include/coreboot_tables.h</span><br><span>@@ -200,7 +200,6 @@</span><br><span> struct cb_gpio gpios[0];</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CB_TAG_CHROMEOS_ACPI 0x0015</span><br><span> #define CB_TAG_VBNV 0x0019</span><br><span> #define CB_TAG_VBOOT_HANDOFF 0x0020</span><br><span> #define CB_TAG_DMA 0x0022</span><br><span>diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h</span><br><span>index 66933e3..bd64cdb 100644</span><br><span>--- a/payloads/libpayload/include/sysinfo.h</span><br><span>+++ b/payloads/libpayload/include/sysinfo.h</span><br><span>@@ -97,8 +97,6 @@</span><br><span> </span><br><span> void *vboot_handoff;</span><br><span> u32 vboot_handoff_size;</span><br><span style="color: hsl(0, 100%, 40%);">- void *chromeos_acpi_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 chromeos_acpi_size;</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_LP_ARCH_X86)</span><br><span> int x86_rom_var_mtrr_index;</span><br><span>diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c</span><br><span>index b879987..2189161 100644</span><br><span>--- a/payloads/libpayload/libc/coreboot.c</span><br><span>+++ b/payloads/libpayload/libc/coreboot.c</span><br><span>@@ -106,14 +106,6 @@</span><br><span> info->gpios[i] = gpios->gpios[i];</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct lb_range *chromeos_acpi = (struct lb_range *) ptr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);</span><br><span style="color: hsl(0, 100%, 40%);">- info->chromeos_acpi_size = chromeos_acpi->range_size;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void cb_parse_mac_addresses(unsigned char *ptr,</span><br><span> struct sysinfo_t *info)</span><br><span> {</span><br><span>@@ -357,9 +349,6 @@</span><br><span> case CB_TAG_GPIO:</span><br><span> cb_parse_gpios(ptr, info);</span><br><span> break;</span><br><span style="color: hsl(0, 100%, 40%);">- case CB_TAG_CHROMEOS_ACPI:</span><br><span style="color: hsl(0, 100%, 40%);">- cb_parse_chromeos_acpi(ptr, info);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span> case CB_TAG_VBNV:</span><br><span> cb_parse_vbnv(ptr, info);</span><br><span> break;</span><br><span>diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h</span><br><span>index 34726ab..6ca0f77 100644</span><br><span>--- a/src/commonlib/include/commonlib/coreboot_tables.h</span><br><span>+++ b/src/commonlib/include/commonlib/coreboot_tables.h</span><br><span>@@ -290,7 +290,6 @@</span><br><span> struct lb_gpio gpios[0];</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define LB_TAG_CHROMEOS_ACPI 0x0015</span><br><span> #define LB_TAG_VBNV 0x0019</span><br><span> #define LB_TAB_VBOOT_HANDOFF 0x0020</span><br><span> #define LB_TAB_DMA 0x0022</span><br><span>diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c</span><br><span>index 6b0e1a0..62b3aaa 100644</span><br><span>--- a/src/lib/coreboot_table.c</span><br><span>+++ b/src/lib/coreboot_table.c</span><br><span>@@ -195,19 +195,6 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lb_chromeos_acpi(struct lb_header *header)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(0, 100%, 40%);">- struct lb_range *chromeos_acpi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- chromeos_acpi = (struct lb_range *)lb_new_record(header);</span><br><span style="color: hsl(0, 100%, 40%);">- chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;</span><br><span style="color: hsl(0, 100%, 40%);">- chromeos_acpi->size = sizeof(*chromeos_acpi);</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,</span><br><span style="color: hsl(0, 100%, 40%);">- &chromeos_acpi->range_size);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void lb_vbnv(struct lb_header *header)</span><br><span> {</span><br><span> #if IS_ENABLED(CONFIG_PC80_SYSTEM)</span><br><span>@@ -547,9 +534,6 @@</span><br><span> /* Record our GPIO settings (ChromeOS specific) */</span><br><span> lb_gpios(head);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* pass along the chromeos_acpi_t buffer address */</span><br><span style="color: hsl(0, 100%, 40%);">- lb_chromeos_acpi(head);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* pass along VBNV offsets in CMOS */</span><br><span> lb_vbnv(head);</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>index b4f7213..bcac3a9 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>@@ -55,6 +55,6 @@</span><br><span> /* ChromeOS specific (0x100 - 0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #endif /* __SOC_STONEYRIDGE_NVS_H__ */</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h</span><br><span>index c7be979..3250aeb 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/nvs.h</span><br><span>@@ -53,6 +53,6 @@</span><br><span> /* ChromeOS specific (0x100 - 0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #endif /* _SOC_APOLLOLAKE_NVS_H_ */</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h</span><br><span>index b4fe65e..bc6f7ec 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h</span><br><span>@@ -19,9 +19,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Offset in Global NVS where this structure lives */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define LPSS_NVS_SIO_DMA1 0</span><br><span> #define LPSS_NVS_I2C1 1</span><br><span> #define LPSS_NVS_I2C2 2</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h</span><br><span>index 21cdb14..715929d 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/nvs.h</span><br><span>@@ -102,7 +102,7 @@</span><br><span> /* Baytrail LPSS (0x1000) */</span><br><span> device_nvs_t dev;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> void acpi_create_gnvs(global_nvs_t *gnvs);</span><br><span> #ifdef __SMM__</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>index 268655e..8ed534e 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Offset in Global NVS where this structure lives */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define LPSS_NVS_SIO_DMA1 0</span><br><span> #define LPSS_NVS_I2C1 1</span><br><span> #define LPSS_NVS_I2C2 2</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>index 89a434b..05831bb 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>@@ -106,7 +106,7 @@</span><br><span> /* LPSS (0x1000) */</span><br><span> device_nvs_t dev;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> void acpi_create_gnvs(global_nvs_t *gnvs);</span><br><span> #if ENV_SMM</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h</span><br><span>index 15240d1..d17b3d4 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h</span><br><span>@@ -19,9 +19,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Offset in Global NVS where this structure lives */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define SIO_NVS_DMA 0</span><br><span> #define SIO_NVS_I2C0 1</span><br><span> #define SIO_NVS_I2C1 2</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h</span><br><span>index 34673d5..2e51e1b 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/nvs.h</span><br><span>@@ -94,7 +94,7 @@</span><br><span> /* Device specific (0x1000) */</span><br><span> device_nvs_t dev;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> void acpi_create_gnvs(global_nvs_t *gnvs);</span><br><span> #ifdef __SMM__</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h</span><br><span>index 6c64f3a..1e55625 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/nvs.h</span><br><span>@@ -46,7 +46,7 @@</span><br><span> /* ChromeOS specific (0x100 - 0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h</span><br><span>index 5bafea6..8eff8cd 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h</span><br><span>@@ -19,9 +19,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Offset in Global NVS where this structure lives */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define LPSS_NVS_SIO_DMA1 0</span><br><span> #define LPSS_NVS_I2C1 1</span><br><span> #define LPSS_NVS_I2C2 2</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h</span><br><span>index 02c9e65..2b7d126 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/device_nvs.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Offset in Global NVS where this structure lives */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define SIO_NVS_I2C0 0</span><br><span> #define SIO_NVS_I2C1 1</span><br><span> #define SIO_NVS_I2C2 2</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h</span><br><span>index bd3610e..53fdded 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/nvs.h</span><br><span>@@ -102,6 +102,6 @@</span><br><span> /* ChromeOS specific (0x100 - 0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h</span><br><span>index 207f763..537139d 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/nvs.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/nvs.h</span><br><span>@@ -154,7 +154,7 @@</span><br><span> /* ChromeOS specific (starts at 0x100)*/</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> /* Used in SMM to find the ACPI GNVS address */</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h</span><br><span>index a0e063c..c8af5b9 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/nvs.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h</span><br><span>@@ -150,7 +150,7 @@</span><br><span> /* ChromeOS specific (starts at 0x100)*/</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> /* Used in SMM to find the ACPI GNVS address */</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h</span><br><span>index a0e063c..c8af5b9 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/nvs.h</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/nvs.h</span><br><span>@@ -150,7 +150,7 @@</span><br><span> /* ChromeOS specific (starts at 0x100)*/</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> /* Used in SMM to find the ACPI GNVS address */</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h</span><br><span>index 8703911..7b9fd24 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/nvs.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/nvs.h</span><br><span>@@ -152,7 +152,7 @@</span><br><span> /* ChromeOS specific (starts at 0x100)*/</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> /* Used in SMM to find the ACPI GNVS address */</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h</span><br><span>index e7d4a8b..fd0d8bc 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/nvs.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/nvs.h</span><br><span>@@ -128,7 +128,7 @@</span><br><span> /* ChromeOS specific (starts at 0x100)*/</span><br><span> chromeos_acpi_t chromeos;</span><br><span> } __packed global_nvs_t;</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(global_nvs_t, chromeos, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> /* Used in SMM to find the ACPI GNVS address */</span><br><span>diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h</span><br><span>index e865c0e..62fa08c 100644</span><br><span>--- a/src/vendorcode/google/chromeos/gnvs.h</span><br><span>+++ b/src/vendorcode/google/chromeos/gnvs.h</span><br><span>@@ -41,6 +41,18 @@</span><br><span> #define ACTIVE_ECFW_RO 0</span><br><span> #define ACTIVE_ECFW_RW 1</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * chromeos_acpi_t portion of ACPI GNVS is assumed to live at</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x100 - 0x1000. When defining global_nvs_t, use check_member</span><br><span style="color: hsl(120, 100%, 40%);">+ * to ensure that it is properly aligned:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GNVS_CHROMEOS_ACPI_OFFSET 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GNVS_DEVICE_NVS_OFFSET 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef struct {</span><br><span> /* ChromeOS specific */</span><br><span> u32 vbt0; // 00 boot reason</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28190">change 28190</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28190"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 </div>
<div style="display:none"> Gerrit-Change-Number: 28190 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Joel Kitching <kitching@google.com> </div>