[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add bootblock_fch_init

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28059 )

Change subject: soc/amd/stoneyridge: Add bootblock_fch_init
......................................................................

soc/amd/stoneyridge: Add bootblock_fch_init

Add a method in bootblock that can be used for printing registers.

BUG=none
TEST=compiled grunt

Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8
Signed-off-by: Raul E Rangel <rrangel at chromium.org>
Reviewed-on: https://review.coreboot.org/28059
Reviewed-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Reviewed-by: Martin Roth <martinroth at google.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved
  Marshall Dawson: Looks good to me, approved



diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 7b2c420..c2440b0 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -106,6 +106,8 @@
 	u32 val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
 
+	bootblock_fch_init();
+
 	/* Initialize any early i2c buses. */
 	i2c_soc_early_init();
 }
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 64b4b46..c6f7791 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -449,6 +449,7 @@
 void xhci_pm_write32(uint8_t reg, uint32_t value);
 uint32_t xhci_pm_read32(uint8_t reg);
 void bootblock_fch_early_init(void);
+void bootblock_fch_init(void);
 /**
  * @brief Save the UMA bize returned by AGESA
  *
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a6219b4..c4b8d04 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -621,6 +621,7 @@
 	}
 }
 
+/* Before console init */
 void bootblock_fch_early_init(void)
 {
 	int reboot = 0;
@@ -643,6 +644,9 @@
 	enable_aoac_devices();
 }
 
+/* After console init */
+void bootblock_fch_init(void) {}
+
 void sb_enable(device_t dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8
Gerrit-Change-Number: 28059
Gerrit-PatchSet: 3
Gerrit-Owner: Raul Rangel <rrangel at chromium.org>
Gerrit-Reviewer: Edward Hill <ecgh at chromium.org>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Raul Rangel <rrangel at chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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