<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/28059">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved
  Marshall Dawson: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add bootblock_fch_init<br><br>Add a method in bootblock that can be used for printing registers.<br><br>BUG=none<br>TEST=compiled grunt<br><br>Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8<br>Signed-off-by: Raul E Rangel <rrangel@chromium.org><br>Reviewed-on: https://review.coreboot.org/28059<br>Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-by: Martin Roth <martinroth@google.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>3 files changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 7b2c420..c2440b0 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -106,6 +106,8 @@</span><br><span>  u32 val = cpuid_eax(1);</span><br><span>      printk(BIOS_DEBUG, "Family_Model: %08x\n", val);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        bootblock_fch_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      /* Initialize any early i2c buses. */</span><br><span>        i2c_soc_early_init();</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 64b4b46..c6f7791 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -449,6 +449,7 @@</span><br><span> void xhci_pm_write32(uint8_t reg, uint32_t value);</span><br><span> uint32_t xhci_pm_read32(uint8_t reg);</span><br><span> void bootblock_fch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_fch_init(void);</span><br><span> /**</span><br><span>  * @brief Save the UMA bize returned by AGESA</span><br><span>  *</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index a6219b4..c4b8d04 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -621,6 +621,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Before console init */</span><br><span> void bootblock_fch_early_init(void)</span><br><span> {</span><br><span>    int reboot = 0;</span><br><span>@@ -643,6 +644,9 @@</span><br><span>        enable_aoac_devices();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* After console init */</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_fch_init(void) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void sb_enable(device_t dev)</span><br><span> {</span><br><span>   printk(BIOS_DEBUG, "%s\n", __func__);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28059">change 28059</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28059"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 </div>
<div style="display:none"> Gerrit-Change-Number: 28059 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Edward Hill <ecgh@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>