[coreboot-gerrit] Change in coreboot[master]: eve: Support PL1 override option

[Lucas Chen (Code Review)]

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28079


Change subject: eve: Support PL1 override option
......................................................................

eve: Support PL1 override option

AltOS DPTF prefers MMIO to control the PL1 setting. However, MSR PL1 also
contributes to the decision of the max PL1 power. In the current design,
the lower value takes effect. In order to align MMIO and MSR settings, a
tdp_pl1_override option is added to override the MSR PL1 limitation.

BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
     2. Verify the MSR PL1 limitation is set from TAT.

Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen at quanta.corp-partner.google.com>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/cpu.c
2 files changed, 6 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28079/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a147d92..8cef686 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -99,6 +99,8 @@
 
 	/* PL2 Override value in Watts */
 	u32 tdp_pl2_override;
+	/* PL1 Override value in Watts */
+	u32 tdp_pl1_override;
 
 	/* SysPL2 Value in Watts */
 	u32 tdp_psyspl2;
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 5535ec6..417c4bc 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -117,7 +117,7 @@
 	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
 	msr_t limit;
 	unsigned int power_unit;
-	unsigned int tdp, min_power, max_power, max_time, tdp_pl2;
+	unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
 	u8 power_limit_1_val;
 	struct device *dev = SA_DEV_ROOT;
 	config_t *conf = dev->chip_info;
@@ -154,7 +154,9 @@
 
 	/* Set long term power limit to TDP */
 	limit.lo = 0;
-	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
+		tdp : (conf->tdp_pl1_override * power_unit));
+	limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
 
 	/* Set PL1 Pkg Power clamp bit */
 	limit.lo |= PKG_POWER_LIMIT_CLAMP;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Gerrit-Change-Number: 28079
Gerrit-PatchSet: 1
Gerrit-Owner: Lucas Chen <lucas.chen at quanta.corp-partner.google.com>
Gerrit-Reviewer: Wei Shun Chang <wei.shun.chang at intel.com>
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