[coreboot-gerrit] Change in coreboot[master]: soc/cn81xx: WIP Add VBOOT support
Philipp Deppenwiese (Code Review)
gerrit at coreboot.org
Sat Aug 11 01:08:37 CEST 2018
Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/28022
Change subject: soc/cn81xx: WIP Add VBOOT support
......................................................................
soc/cn81xx: WIP Add VBOOT support
* Add VERSTAGE and VBOOT_WORk to memlayout.
* Add hard and soft reset.
* Add missing makefile and kconfig includes.
Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
M src/soc/cavium/cn81xx/Kconfig
M src/soc/cavium/cn81xx/Makefile.inc
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
A src/soc/cavium/cn81xx/include/soc/reset.h
A src/soc/cavium/cn81xx/reset.c
5 files changed, 82 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28022/1
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index edc9480..0a691cf 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -5,6 +5,7 @@
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
+ select ARM64_USE_ARM_TRUSTED_FIRMWARE
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_PL011
select GENERIC_UDELAY
@@ -14,9 +15,15 @@
select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS
select MMCONF_SUPPORT
select PCI
+ select HAVE_HARD_RESET
if SOC_CAVIUM_CN81XX
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_RETURN_FROM_VERSTAGE
+ select VBOOT_STARTS_IN_BOOTBLOCK
+
config ARM64_BL31_EXTERNAL_FILE
string
default "3rdparty/blobs/soc/cavium/cn81xx/bl31.elf"
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index 845ac34..c58c07e 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -25,11 +25,25 @@
bootblock-y += spi.c
bootblock-y += uart.c
bootblock-y += cpu.c
+bootblock-y += reset.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
################################################################################
+# verstage
+
+verstage-y += twsi.c
+verstage-y += clock.c
+verstage-y += gpio.c
+verstage-y += timer.c
+verstage-y += spi.c
+verstage-y += uart.c
+verstage-$(CONFIG_DRIVERS_UART) += uart.c
+verstage-y += cbmem.c
+verstage-y += reset.c
+
+################################################################################
# romstage
romstage-y += twsi.c
@@ -39,16 +53,12 @@
romstage-y += spi.c
romstage-y += uart.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
-romstage-< += cpu.c
+romstage-y += cbmem.c
+romstage-y += reset.c
romstage-y += sdram.c
romstage-y += mmu.c
-romstage-y += ../common/cbmem.c
-# BDK coreboot interface
-romstage-y += ../common/bdk-coreboot.c
-
-
################################################################################
# ramstage
@@ -64,12 +74,11 @@
ramstage-y += cpu.c
ramstage-y += cpu_secondary.S
ramstage-y += ecam0.c
+ramstage-y += cbmem.c
+ramstage-y += reset.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
-# BDK coreboot interface
-ramstage-y += ../common/bdk-coreboot.c
-
BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index b80d152..e3bf61f 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -28,14 +28,18 @@
/* Insecure region 1MiB - TOP OF DRAM */
/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
SRAM_START(BOOTROM_OFFSET)
+
STACK(BOOTROM_OFFSET, 16K)
TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)
PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
-
BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+ VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
+ VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K)
ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
+
SRAM_END(BOOTROM_OFFSET + 0x80000)
+
TTB(BOOTROM_OFFSET + 0x80000, 512K)
RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
/* Stack for secondary CPUs */
diff --git a/src/soc/cavium/cn81xx/include/soc/reset.h b/src/soc/cavium/cn81xx/include/soc/reset.h
new file mode 100644
index 0000000..6af3059
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/reset.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_RESET_H
+#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_RESET_H
+
+#define RST_SOFT_RST 0x87e006001680
+
+void do_soft_reset(void);
+void do_hard_reset(void);
+
+#endif
diff --git a/src/soc/cavium/cn81xx/reset.c b/src/soc/cavium/cn81xx/reset.c
new file mode 100644
index 0000000..929ed3f
--- /dev/null
+++ b/src/soc/cavium/cn81xx/reset.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <soc/reset.h>
+#include <device/i2c_simple.h>
+
+void do_soft_reset(void)
+{
+ write64((void *)RST_SOFT_RST, 1);
+}
+
+void do_hard_reset(void)
+{
+
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad
Gerrit-Change-Number: 28022
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
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