<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28022">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cn81xx: WIP Add VBOOT support<br><br>* Add VERSTAGE and VBOOT_WORk to memlayout.<br>* Add hard and soft reset.<br>* Add missing makefile and kconfig includes.<br><br>Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>M src/soc/cavium/cn81xx/Kconfig<br>M src/soc/cavium/cn81xx/Makefile.inc<br>M src/soc/cavium/cn81xx/include/soc/memlayout.ld<br>A src/soc/cavium/cn81xx/include/soc/reset.h<br>A src/soc/cavium/cn81xx/reset.c<br>5 files changed, 82 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28022/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig</span><br><span>index edc9480..0a691cf 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Kconfig</span><br><span>+++ b/src/soc/cavium/cn81xx/Kconfig</span><br><span>@@ -5,6 +5,7 @@</span><br><span> select ARCH_RAMSTAGE_ARMV8_64</span><br><span> select ARCH_ROMSTAGE_ARMV8_64</span><br><span> select ARCH_VERSTAGE_ARMV8_64</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARM64_USE_ARM_TRUSTED_FIRMWARE</span><br><span> select BOOTBLOCK_CONSOLE</span><br><span> select DRIVERS_UART_PL011</span><br><span> select GENERIC_UDELAY</span><br><span>@@ -14,9 +15,15 @@</span><br><span> select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS</span><br><span> select MMCONF_SUPPORT</span><br><span> select PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_HARD_RESET</span><br><span> </span><br><span> if SOC_CAVIUM_CN81XX</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_RETURN_FROM_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config ARM64_BL31_EXTERNAL_FILE</span><br><span> string</span><br><span> default "3rdparty/blobs/soc/cavium/cn81xx/bl31.elf"</span><br><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index 845ac34..c58c07e 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -25,11 +25,25 @@</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += uart.c</span><br><span> bootblock-y += cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += reset.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span> bootblock-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> endif</span><br><span> </span><br><span> ################################################################################</span><br><span style="color: hsl(120, 100%, 40%);">+# verstage</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += twsi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += reset.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+################################################################################</span><br><span> # romstage</span><br><span> </span><br><span> romstage-y += twsi.c</span><br><span>@@ -39,16 +53,12 @@</span><br><span> romstage-y += spi.c</span><br><span> romstage-y += uart.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-< += cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += reset.c</span><br><span> </span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += mmu.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../common/cbmem.c</span><br><span style="color: hsl(0, 100%, 40%);">-# BDK coreboot interface</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../common/bdk-coreboot.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> ################################################################################</span><br><span> # ramstage</span><br><span> </span><br><span>@@ -64,12 +74,11 @@</span><br><span> ramstage-y += cpu.c</span><br><span> ramstage-y += cpu_secondary.S</span><br><span> ramstage-y += ecam0.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += reset.c</span><br><span> </span><br><span> ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-# BDK coreboot interface</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += ../common/bdk-coreboot.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>index b80d152..e3bf61f 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>@@ -28,14 +28,18 @@</span><br><span> /* Insecure region 1MiB - TOP OF DRAM */</span><br><span> /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */</span><br><span> SRAM_START(BOOTROM_OFFSET)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> STACK(BOOTROM_OFFSET, 16K)</span><br><span> TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)</span><br><span> PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)</span><br><span> PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K)</span><br><span> ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> SRAM_END(BOOTROM_OFFSET + 0x80000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> TTB(BOOTROM_OFFSET + 0x80000, 512K)</span><br><span> RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)</span><br><span> /* Stack for secondary CPUs */</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/reset.h b/src/soc/cavium/cn81xx/include/soc/reset.h</span><br><span>new file mode 100644</span><br><span>index 0000000..6af3059</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/reset.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_RESET_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_RESET_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_SOFT_RST 0x87e006001680</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void do_soft_reset(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void do_hard_reset(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/cavium/cn81xx/reset.c b/src/soc/cavium/cn81xx/reset.c</span><br><span>new file mode 100644</span><br><span>index 0000000..929ed3f</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/cn81xx/reset.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/i2c_simple.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void do_soft_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write64((void *)RST_SOFT_RST, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28022">change 28022</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28022"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad </div>
<div style="display:none"> Gerrit-Change-Number: 28022 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>