[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add PMxC0 reset status to boot log

[Edward Hill (Code Review)]

Edward Hill has uploaded this change for review. ( https://review.coreboot.org/28020


Change subject: amd/stoneyridge: Add PMxC0 reset status to boot log
......................................................................

amd/stoneyridge: Add PMxC0 reset status to boot log

Print the PMxC0 S5/Reset status bits to the console.

TEST=Inspect console for Grunt
BUG=b:110788201

Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Signed-off-by: Edward Hill <ecgh at chromium.org>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 37 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/28020/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 64b4b46..80671df 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -91,6 +91,7 @@
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
 #define PM_RST_CTRL1			0xbe
 #define   SLPTYPE_CONTROL_EN		BIT(5)
+#define PM_RST_STATUS			0xc0
 #define PM_PMIO_DEBUG			0xd2
 #define PM_MANUAL_RESET			0xd3
 #define PM_HUD_SD_FLASH_CTRL		0xe7
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a6219b4..f406ff4 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -789,6 +789,41 @@
 	print_pm1_status(pm1_sts);
 }
 
+static void sb_print_pmxc0_status(void)
+{
+	/* PMxC0 S5/Reset Status shows the source of previous reset. */
+	uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
+
+	static const char *const pmxc0_status_bits[] = {
+		[0] = "ThermalTrip",
+		[1] = "FourSecondPwrBtn",
+		[2] = "Shutdown",
+		[3] = "ThermalTripFromTemp",
+		[4] = "RemotePowerDownFromASF",
+		[5] = "ShutDownFan0",
+		[16] = "UserRst",
+		[17] = "SoftPciRst",
+		[18] = "DoInit",
+		[19] = "DoReset",
+		[20] = "DoFullReset",
+		[21] = "SleepReset",
+		[22] = "KbReset",
+		[23] = "LtReset",
+		[24] = "FailBootRst",
+		[25] = "WatchdogIssueReset",
+		[26] = "RemoteResetFromASF",
+		[27] = "SyncFlood",
+		[28] = "HangReset",
+		[29] = "EcWatchdogRst",
+		[31] = "BIT31",
+	};
+
+	printk(BIOS_SPEW, "PMxC0 STATUS: 0x%x ", pmxc0_status);
+	print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
+			      pmxc0_status_bits);
+	printk(BIOS_SPEW, "\n");
+}
+
 static int get_index_bit(uint32_t value, uint16_t limit)
 {
 	uint16_t i;
@@ -842,6 +877,7 @@
 {
 	sb_init_acpi_ports();
 	sb_clear_pm1_status();
+	sb_print_pmxc0_status();
 }
 
 void southbridge_final(void *chip_info)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Gerrit-Change-Number: 28020
Gerrit-PatchSet: 1
Gerrit-Owner: Edward Hill <ecgh at chromium.org>
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