<p>Edward Hill has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28020">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add PMxC0 reset status to boot log<br><br>Print the PMxC0 S5/Reset status bits to the console.<br><br>TEST=Inspect console for Grunt<br>BUG=b:110788201<br><br>Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb<br>Signed-off-by: Edward Hill <ecgh@chromium.org><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 37 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/28020/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 64b4b46..80671df 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -91,6 +91,7 @@</span><br><span> #define PM_ACPI_RTC_WAKE_EN BIT(29)</span><br><span> #define PM_RST_CTRL1 0xbe</span><br><span> #define SLPTYPE_CONTROL_EN BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_RST_STATUS 0xc0</span><br><span> #define PM_PMIO_DEBUG 0xd2</span><br><span> #define PM_MANUAL_RESET 0xd3</span><br><span> #define PM_HUD_SD_FLASH_CTRL 0xe7</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index a6219b4..f406ff4 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -789,6 +789,41 @@</span><br><span> print_pm1_status(pm1_sts);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void sb_print_pmxc0_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMxC0 S5/Reset Status shows the source of previous reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const pmxc0_status_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [0] = "ThermalTrip",</span><br><span style="color: hsl(120, 100%, 40%);">+ [1] = "FourSecondPwrBtn",</span><br><span style="color: hsl(120, 100%, 40%);">+ [2] = "Shutdown",</span><br><span style="color: hsl(120, 100%, 40%);">+ [3] = "ThermalTripFromTemp",</span><br><span style="color: hsl(120, 100%, 40%);">+ [4] = "RemotePowerDownFromASF",</span><br><span style="color: hsl(120, 100%, 40%);">+ [5] = "ShutDownFan0",</span><br><span style="color: hsl(120, 100%, 40%);">+ [16] = "UserRst",</span><br><span style="color: hsl(120, 100%, 40%);">+ [17] = "SoftPciRst",</span><br><span style="color: hsl(120, 100%, 40%);">+ [18] = "DoInit",</span><br><span style="color: hsl(120, 100%, 40%);">+ [19] = "DoReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [20] = "DoFullReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [21] = "SleepReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [22] = "KbReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [23] = "LtReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [24] = "FailBootRst",</span><br><span style="color: hsl(120, 100%, 40%);">+ [25] = "WatchdogIssueReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [26] = "RemoteResetFromASF",</span><br><span style="color: hsl(120, 100%, 40%);">+ [27] = "SyncFlood",</span><br><span style="color: hsl(120, 100%, 40%);">+ [28] = "HangReset",</span><br><span style="color: hsl(120, 100%, 40%);">+ [29] = "EcWatchdogRst",</span><br><span style="color: hsl(120, 100%, 40%);">+ [31] = "BIT31",</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "PMxC0 STATUS: 0x%x ", pmxc0_status);</span><br><span style="color: hsl(120, 100%, 40%);">+ print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,</span><br><span style="color: hsl(120, 100%, 40%);">+ pmxc0_status_bits);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static int get_index_bit(uint32_t value, uint16_t limit)</span><br><span> {</span><br><span> uint16_t i;</span><br><span>@@ -842,6 +877,7 @@</span><br><span> {</span><br><span> sb_init_acpi_ports();</span><br><span> sb_clear_pm1_status();</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_print_pmxc0_status();</span><br><span> }</span><br><span> </span><br><span> void southbridge_final(void *chip_info)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28020">change 28020</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb </div>
<div style="display:none"> Gerrit-Change-Number: 28020 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Edward Hill <ecgh@chromium.org> </div>