[coreboot-gerrit] Change in coreboot[master]: src: Fix typo

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27988 )

Change subject: src: Fix typo
......................................................................


Patch Set 1:

(5 comments)

https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c:

https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c@927
PS1, Line 927: 		/* On Family15h processors, the value for the specific CS being targeted
line over 80 characters


https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/amdmct/wrappers/mcti_d.c
File src/northbridge/amd/amdmct/wrappers/mcti_d.c:

https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/amdmct/wrappers/mcti_d.c@173
PS1, Line 173: 		//val = 2;	/* Override faulty SPD checksum (DIMM will be enabled), continue current node initialization */
line over 80 characters


https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/lx/northbridgeinit.c
File src/northbridge/amd/lx/northbridgeinit.c:

https://review.coreboot.org/#/c/27988/1/src/northbridge/amd/lx/northbridgeinit.c@275
PS1, Line 275: 		/* So we need a high page aligned address (pah) and low page aligned address (pal)
line over 80 characters


https://review.coreboot.org/#/c/27988/1/src/northbridge/via/vx900/raminit_ddr3.c
File src/northbridge/via/vx900/raminit_ddr3.c:

https://review.coreboot.org/#/c/27988/1/src/northbridge/via/vx900/raminit_ddr3.c@1227
PS1, Line 1227: static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays,
"foo * bar" should be "foo *bar"


https://review.coreboot.org/#/c/27988/1/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
File src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h:

https://review.coreboot.org/#/c/27988/1/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h@41
PS1, Line 41:  *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers
line over 80 characters



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Gerrit-Change-Number: 27988
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 09 Aug 2018 16:57:47 +0000
Gerrit-HasComments: Yes
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