[coreboot-gerrit] Change in coreboot[master]: riscv: update misaligned memory access exception handling

[Xiang Wang (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/27972

to look at the new patch set (#2).

Change subject: riscv: update misaligned memory access exception handling
......................................................................

riscv: update misaligned memory access exception handling

Support for more situations: floating point, compressed instructions,
etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ
to support that reading the page which is executable-only (R=0 X=1).

Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/fp_asm.S
M src/arch/riscv/include/arch/exception.h
M src/arch/riscv/include/vm.h
A src/arch/riscv/misaligend.c
M src/arch/riscv/trap_handler.c
6 files changed, 617 insertions(+), 65 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Gerrit-Change-Number: 27972
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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