[coreboot-gerrit] Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
......................................................................


Patch Set 1:

(4 comments)

https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@176
PS1, Line 176: 		int regnum = ((insn >> match->reg_shift) & match->reg_mask) + \
Avoid unnecessary line continuations


https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@185
PS1, Line 185: 				buff.b[i] = mprv_read_u8((uint8_t *) \
Avoid unnecessary line continuations


https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@242
PS1, Line 242: 				mprv_write_u8((uint8_t *)(tf->badvaddr + i), \
Avoid unnecessary line continuations


https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c
File src/arch/riscv/trap_handler.c:

https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c@191
PS1, Line 191: 	write_csr(sepc, read_csr(mepc));
'sepc' may be misspelled - perhaps 'spec'?



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Gerrit-Change-Number: 27972
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 09 Aug 2018 08:21:33 +0000
Gerrit-HasComments: Yes
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