[coreboot-gerrit] Change in coreboot[master]: cbmem: rename vdat to chromeos_acpi
Joel Kitching (Code Review)
gerrit at coreboot.org
Tue Aug 7 06:49:43 CEST 2018
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/27888
Change subject: cbmem: rename vdat to chromeos_acpi
......................................................................
cbmem: rename vdat to chromeos_acpi
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.
Within the chromeos_acpi_t structure, there is a member
called vdat. This (currently) holds a VbSharedDataHeader.
Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.
Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.
BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722
Signed-off-by: Joel Kitching <kitching at google.com>
Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
---
M 3rdparty/blobs
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
M src/arch/x86/smbios.c
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
M src/vendorcode/google/chromeos/gnvs.c
M src/vendorcode/google/chromeos/gnvs.h
9 files changed, 43 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27888/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
index 372012e..8e9f99b 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 372012e8e1d0d01f3e77ff73b118665b41ff68b6
+Subproject commit 8e9f99b3e60d0ffe8b67cc93ea4ab1b9ed191e45
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 6b6d1b4..4cf57c5 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -200,7 +200,7 @@
struct cb_gpio gpios[0];
};
-#define CB_TAG_VDAT 0x0015
+#define CB_TAG_CHROMEOS_ACPI 0x0015
#define CB_TAG_VBNV 0x0019
#define CB_TAG_VBOOT_HANDOFF 0x0020
#define CB_TAG_DMA 0x0022
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index f221a15..66933e3 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -97,8 +97,8 @@
void *vboot_handoff;
u32 vboot_handoff_size;
- void *vdat_addr;
- u32 vdat_size;
+ void *chromeos_acpi_addr;
+ u32 chromeos_acpi_size;
#if IS_ENABLED(CONFIG_LP_ARCH_X86)
int x86_rom_var_mtrr_index;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index d831b96..b879987 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -106,12 +106,12 @@
info->gpios[i] = gpios->gpios[i];
}
-static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)
{
- struct lb_range *vdat = (struct lb_range *) ptr;
+ struct lb_range *chromeos_acpi = (struct lb_range *) ptr;
- info->vdat_addr = phys_to_virt(vdat->range_start);
- info->vdat_size = vdat->range_size;
+ info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);
+ info->chromeos_acpi_size = chromeos_acpi->range_size;
}
static void cb_parse_mac_addresses(unsigned char *ptr,
@@ -357,8 +357,8 @@
case CB_TAG_GPIO:
cb_parse_gpios(ptr, info);
break;
- case CB_TAG_VDAT:
- cb_parse_vdat(ptr, info);
+ case CB_TAG_CHROMEOS_ACPI:
+ cb_parse_chromeos_acpi(ptr, info);
break;
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 582ae8d..8dad4af 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -367,7 +367,11 @@
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
/* SMBIOS offsets start at 1 rather than 0 */
- vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
+ chromeos_acpi_t *chromeos_acpi;
+ uint32_t *chromeos_acpi_size;
+ acpi_get_chromeos_acpi_info((uint64_t *)&chromeos_acpi,
+ (uint32_t *)&chromeos_acpi_size);
+ chromeos_acpi->vbt10 = (u32)t->eos + (version_offset - 1);
#endif
#endif /* CONFIG_CHROMEOS */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 806dfc7..34726ab 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -290,7 +290,7 @@
struct lb_gpio gpios[0];
};
-#define LB_TAG_VDAT 0x0015
+#define LB_TAG_CHROMEOS_ACPI 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 2d74c8e..6b0e1a0 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -195,15 +195,16 @@
}
}
-static void lb_vdat(struct lb_header *header)
+static void lb_chromeos_acpi(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- struct lb_range *vdat;
+ struct lb_range *chromeos_acpi;
- vdat = (struct lb_range *)lb_new_record(header);
- vdat->tag = LB_TAG_VDAT;
- vdat->size = sizeof(*vdat);
- acpi_get_vdat_info(&vdat->range_start, &vdat->range_size);
+ chromeos_acpi = (struct lb_range *)lb_new_record(header);
+ chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
+ chromeos_acpi->size = sizeof(*chromeos_acpi);
+ acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
+ &chromeos_acpi->range_size);
#endif
}
@@ -546,8 +547,8 @@
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
- /* pass along the VDAT buffer address */
- lb_vdat(head);
+ /* pass along the chromeos_acpi_t buffer address */
+ lb_chromeos_acpi(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c
index a278b41..b3c71e4 100644
--- a/src/vendorcode/google/chromeos/gnvs.c
+++ b/src/vendorcode/google/chromeos/gnvs.c
@@ -27,40 +27,41 @@
#include "chromeos.h"
#include "gnvs.h"
-chromeos_acpi_t *vboot_data = NULL;
+chromeos_acpi_t *chromeos_acpi = NULL;
static u32 me_hash_saved[8];
-void chromeos_init_vboot(chromeos_acpi_t *chromeos)
+void chromeos_init_vboot(chromeos_acpi_t *init)
{
- vboot_data = chromeos;
+ chromeos_acpi = init;
/* Copy saved ME hash into NVS */
- memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh));
+ memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh));
struct vboot_handoff *vboot_handoff;
if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0)
- memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0],
- ARRAY_SIZE(chromeos->vdat));
+ memcpy(&chromeos_acpi->vdat[0], &vboot_handoff->shared_data[0],
+ ARRAY_SIZE(chromeos_acpi->vdat));
- chromeos_ram_oops_init(chromeos);
+ chromeos_ram_oops_init(chromeos_acpi);
}
void chromeos_set_me_hash(u32 *hash, int len)
{
- if ((len*sizeof(u32)) > sizeof(vboot_data->mehh))
+ if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh))
return;
/* Copy to NVS or save until it is ready */
- if (vboot_data)
+ if (chromeos_acpi)
/* This does never happen! */
- memcpy(vboot_data->mehh, hash, len*sizeof(u32));
+ memcpy(chromeos_acpi->mehh, hash, len*sizeof(u32));
else
memcpy(me_hash_saved, hash, len*sizeof(u32));
}
-void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size)
+void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr,
+ uint32_t *chromeos_acpi_size)
{
- *vdat_addr = (intptr_t)vboot_data;
- *vdat_size = sizeof(*vboot_data);
+ *chromeos_acpi_addr = (intptr_t)chromeos_acpi;
+ *chromeos_acpi_size = sizeof(*chromeos_acpi);
}
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index 82cd409..346ac43 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -53,7 +53,7 @@
u32 vbt7; // 18e active main firmware type
u32 vbt8; // 192 recovery reason
u32 vbt9; // 196 fmap base address
- u8 vdat[3072]; // 19a
+ u8 vdat[3072]; // 19a VDAT space filled by verified boot
u32 vbt10; // d9a smbios bios version
u32 mehh[8]; // d9e management engine hash
u32 ramoops_base; // dbe ramoops base address
@@ -61,9 +61,9 @@
u8 pad[314]; // dc6-eff
} __packed chromeos_acpi_t;
-extern chromeos_acpi_t *vboot_data;
-void chromeos_init_vboot(chromeos_acpi_t *chromeos);
+void chromeos_init_vboot(chromeos_acpi_t *init);
void chromeos_set_me_hash(u32*, int);
-void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size);
+void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr,
+ uint32_t *chromeos_acpi_size);
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Gerrit-Change-Number: 27888
Gerrit-PatchSet: 1
Gerrit-Owner: Joel Kitching <kitching at google.com>
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