[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/27814


Change subject: vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
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vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config

From doc 571118, the bit 5 of OdtConfig is nWR config.

Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27814/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
index c25fd40..0329c93 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
@@ -474,6 +474,7 @@
   1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3:  X - Don't Care. [4] TX ODT. DDR3L only:
   0 = RZQ/4 (60 Ohms)  = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS,   1 = RZQ/2 (120
   Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4:   X = Don't Care
+  [5] nWR config: 0 - nWR6, 1 - nWR24.
 **/
   UINT8                       Ch0_OdtConfig;
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Gerrit-Change-Number: 27814
Gerrit-PatchSet: 1
Gerrit-Owner: Kane Chen <kane.chen at intel.com>
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