[coreboot-gerrit] Change in coreboot[master]: riscv: add suport to check machine length at runtime

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27770


Change subject: riscv: add suport to check machine length at runtime
......................................................................

riscv: add suport to check machine length at runtime

Highest two bits of misa can be used to check machine length. Add code to support this.

Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/include/arch/cpu.h
1 file changed, 12 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27770/1

diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index 6008c75..d8a49b8 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -51,5 +51,17 @@
 	return read_csr(misa) & (1 << (ext - 'A'));
 }
 
+static inline int xlen(void)
+{
+	long t = read_csr(misa);
+	if (t < 0) {
+		t = t << 1;
+		if (t < 0)
+			return 128;
+		return 64;
+	}
+	return 32;
+}
+
 struct cpu_info *cpu_info(void);
 #endif /* __ARCH_CPU_H__ */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25
Gerrit-Change-Number: 27770
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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