[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/22261 )

Change subject: nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width
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Patch Set 2:

is this only valid for non-ECC memory? for non-ECC DDR3 this is true, but I'm not sure about the ECC case


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I3b83a098205455b1c820d0436c6984938f261466
Gerrit-Change-Number: 22261
Gerrit-PatchSet: 2
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Felix Held <felix-coreboot at felixheld.de>
Gerrit-Comment-Date: Sat, 28 Apr 2018 19:51:58 +0000
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