[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Switch to common block for GSPI
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu Apr 26 10:49:02 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25863
Change subject: soc/intel/cannonlake: Switch to common block for GSPI
......................................................................
soc/intel/cannonlake: Switch to common block for GSPI
>From cannonlake onwards we'll use GSPI functionality from common block
which was created in previous patch and remove gspi.c file from soc. We
need to implement/move one soc specific function which is moved to
chip_config.c which returns soc specific configuration for gspi.
This will reduce redundant copy of code which is common across multiple
soc.
BUG=none
BRANCH=none
TEST=Coreboot builds with different board configuration. Also coreboot
boots with these changes on cannonlake board.
Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip_config.c
D src/soc/intel/cannonlake/gspi.c
4 files changed, 25 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/25863/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 55f2ea8..c9b3bd3 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -54,7 +54,7 @@
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
- select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C_V2
select SOC_INTEL_COMMON_BLOCK_LPC
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index afebb24..1e463c2 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -13,16 +13,16 @@
bootblock-y += bootblock/pch.c
bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c
+bootblock-y += chip_config.c
bootblock-y += gpio.c
-bootblock-y += gspi.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
+romstage-y += chip_config.c
romstage-y += gpio.c
-romstage-y += gspi.c
romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c
@@ -36,7 +36,6 @@
ramstage-y += finalize.c
ramstage-y += gpio.c
ramstage-y += graphics.c
-ramstage-y += gspi.c
ramstage-y += gpio.c
ramstage-y += lpc.c
ramstage-y += memmap.c
@@ -61,7 +60,7 @@
postcar-y += pmutil.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
-verstage-y += gspi.c
+verstage-y += chip_config.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
index 191d0d8..230d205 100644
--- a/src/soc/intel/cannonlake/chip_config.c
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelbasecode/lockdown.h>
-
+#include <intelblocks/gspi.h>
/*
* This function will return SOC specific lockdown configuration.
* Function can return 3 possible values:
@@ -28,7 +28,7 @@
int soc_get_lockdown_config(void)
{
const struct soc_intel_cannonlake_config *config;
- struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
if (dev == NULL || dev->chip_info == NULL)
return -1;
@@ -53,3 +53,22 @@
return &config->i2c[bus];
}
+
+const struct gspi_cfg *gspi_get_soc_cfg(void)
+{
+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;
+ int devfn = SA_DEVFN_ROOT;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->gspi[0];
+}
+
+
diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c
deleted file mode 100644
index e4f682d..0000000
--- a/src/soc/intel/cannonlake/gspi.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <device/device.h>
-#include <intelblocks/gspi.h>
-#include <intelblocks/spi.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include "chip.h"
-
-const struct gspi_cfg *gspi_get_soc_cfg(void)
-{
- DEVTREE_CONST struct soc_intel_cannonlake_config *config;
- int devfn = SA_DEVFN_ROOT;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
-
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->gspi[0];
-}
-
-uintptr_t gspi_get_soc_early_base(void)
-{
- return EARLY_GSPI_BASE_ADDRESS;
-}
-
-/*
- * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
- * the bus # accordingly when referring to SPI / GSPI bus numbers.
- */
-#define GSPI_TO_SPI_BUS(x) ((x) + 1)
-#define SPI_TO_GSPI_BUS(x) ((x) - 1)
-
-int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
-{
- if (spi_bus == 0)
- return -1;
-
- *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
- if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
- return -1;
-
- return 0;
-}
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
- if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
- return -1;
-
- return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155
Gerrit-Change-Number: 25863
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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