<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25863">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Switch to common block for GSPI<br><br>From cannonlake onwards we'll use GSPI functionality from common block<br>which was created in previous patch and remove gspi.c file from soc. We<br>need to implement/move one soc specific function which is moved to<br>chip_config.c which returns soc specific configuration for gspi.<br><br>This will reduce redundant copy of code which is common across multiple<br>soc.<br><br>BUG=none<br>BRANCH=none<br>TEST=Coreboot builds with different board configuration. Also coreboot<br>boots with these changes on cannonlake board.<br><br>Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip_config.c<br>D src/soc/intel/cannonlake/gspi.c<br>4 files changed, 25 insertions(+), 79 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/25863/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 55f2ea8..c9b3bd3 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -54,7 +54,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span> select SOC_INTEL_COMMON_BLOCK_GRAPHICS</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3</span><br><span> select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span> select SOC_INTEL_COMMON_BLOCK_I2C_V2</span><br><span> select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index afebb24..1e463c2 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -13,16 +13,16 @@</span><br><span> bootblock-y += bootblock/pch.c</span><br><span> bootblock-y += pmutil.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += chip_config.c</span><br><span> bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gspi.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += chip_config.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gspi.c</span><br><span> romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += pmutil.c</span><br><span>@@ -36,7 +36,6 @@</span><br><span> ramstage-y += finalize.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gspi.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += lpc.c</span><br><span> ramstage-y += memmap.c</span><br><span>@@ -61,7 +60,7 @@</span><br><span> postcar-y += pmutil.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += chip_config.c</span><br><span> verstage-y += pmutil.c</span><br><span> verstage-y += spi.c</span><br><span> verstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>index 191d0d8..230d205 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelbasecode/lockdown.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span> /*</span><br><span> * This function will return SOC specific lockdown configuration.</span><br><span> * Function can return 3 possible values:</span><br><span>@@ -28,7 +28,7 @@</span><br><span> int soc_get_lockdown_config(void)</span><br><span> {</span><br><span> const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span> </span><br><span> if (dev == NULL || dev->chip_info == NULL)</span><br><span> return -1;</span><br><span>@@ -53,3 +53,22 @@</span><br><span> </span><br><span> return &config->i2c[bus];</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct gspi_cfg *gspi_get_soc_cfg(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = SA_DEVFN_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return &config->gspi[0];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c</span><br><span>deleted file mode 100644</span><br><span>index e4f682d..0000000</span><br><span>--- a/src/soc/intel/cannonlake/gspi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,72 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <assert.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/gspi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct gspi_cfg *gspi_get_soc_cfg(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- DEVTREE_CONST struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- int devfn = SA_DEVFN_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(0, 100%, 40%);">- __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return &config->gspi[0];</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t gspi_get_soc_early_base(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return EARLY_GSPI_BASE_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span style="color: hsl(0, 100%, 40%);">- * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GSPI_TO_SPI_BUS(x) ((x) + 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_TO_GSPI_BUS(x) ((x) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (spi_bus == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);</span><br><span style="color: hsl(0, 100%, 40%);">- if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25863">change 25863</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25863"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155 </div>
<div style="display:none"> Gerrit-Change-Number: 25863 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>