[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Create a common gspi V3 block

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25862


Change subject: soc/intel/common/block: Create a common gspi V3 block
......................................................................

soc/intel/common/block: Create a common gspi V3 block

There is already GSPI block available in common and this patch tries to
take common functionality from existing soc and tries to push it into
new block named gspi_v3.

This will remove code which lies inside soc folder but still can be used
as common code across multiple soc. This is applicable from cannonlake
onwards only. To select GSPI from common block instead of using it from
SOC, select "SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3" inside Kconfig.

BUG=none
BRANCH=none
TEST=code is compiling with different configurations.

Change-Id: Ie8573c4b487394893b467bddccb702d4942a4b87
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
A src/soc/intel/common/block/gspi_v3/Kconfig
A src/soc/intel/common/block/gspi_v3/Makefile.inc
A src/soc/intel/common/block/gspi_v3/gspi.c
3 files changed, 64 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25862/1

diff --git a/src/soc/intel/common/block/gspi_v3/Kconfig b/src/soc/intel/common/block/gspi_v3/Kconfig
new file mode 100644
index 0000000..88ced7b
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/Kconfig
@@ -0,0 +1,8 @@
+config SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3
+	bool
+	default n
+	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+	help
+	  Intel Processor Common GSPI support for cannonlake onwards. Enabling
+	  this feature requires soc to implement function which returns soc
+	  based GSPI configuration.
diff --git a/src/soc/intel/common/block/gspi_v3/Makefile.inc b/src/soc/intel/common/block/gspi_v3/Makefile.inc
new file mode 100644
index 0000000..128e0ff
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
diff --git a/src/soc/intel/common/block/gspi_v3/gspi.c b/src/soc/intel/common/block/gspi_v3/gspi.c
new file mode 100644
index 0000000..e9d1f78
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/gspi.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/spi.h>
+#include <soc/iomap.h>
+
+uintptr_t gspi_get_soc_early_base(void)
+{
+	return EARLY_GSPI_BASE_ADDRESS;
+}
+
+/*
+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
+ * the bus # accordingly when referring to SPI / GSPI bus numbers.
+ */
+#define GSPI_TO_SPI_BUS(x)	((x) + 1)
+#define SPI_TO_GSPI_BUS(x)	((x) - 1)
+
+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
+{
+	if (spi_bus == 0)
+		return -1;
+
+	*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
+	if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+		return -1;
+
+	return 0;
+}
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+	if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+		return -1;
+
+	return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie8573c4b487394893b467bddccb702d4942a4b87
Gerrit-Change-Number: 25862
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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