<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25862">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Create a common gspi V3 block<br><br>There is already GSPI block available in common and this patch tries to<br>take common functionality from existing soc and tries to push it into<br>new block named gspi_v3.<br><br>This will remove code which lies inside soc folder but still can be used<br>as common code across multiple soc. This is applicable from cannonlake<br>onwards only. To select GSPI from common block instead of using it from<br>SOC, select "SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3" inside Kconfig.<br><br>BUG=none<br>BRANCH=none<br>TEST=code is compiling with different configurations.<br><br>Change-Id: Ie8573c4b487394893b467bddccb702d4942a4b87<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>A src/soc/intel/common/block/gspi_v3/Kconfig<br>A src/soc/intel/common/block/gspi_v3/Makefile.inc<br>A src/soc/intel/common/block/gspi_v3/gspi.c<br>3 files changed, 64 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25862/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/gspi_v3/Kconfig b/src/soc/intel/common/block/gspi_v3/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..88ced7b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/gspi_v3/Kconfig</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Processor Common GSPI support for cannonlake onwards. Enabling</span><br><span style="color: hsl(120, 100%, 40%);">+ this feature requires soc to implement function which returns soc</span><br><span style="color: hsl(120, 100%, 40%);">+ based GSPI configuration.</span><br><span>diff --git a/src/soc/intel/common/block/gspi_v3/Makefile.inc b/src/soc/intel/common/block/gspi_v3/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..128e0ff</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/gspi_v3/Makefile.inc</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c</span><br><span>diff --git a/src/soc/intel/common/block/gspi_v3/gspi.c b/src/soc/intel/common/block/gspi_v3/gspi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e9d1f78</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/gspi_v3/gspi.c</span><br><span>@@ -0,0 +1,52 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gspi_get_soc_early_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return EARLY_GSPI_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span style="color: hsl(120, 100%, 40%);">+ * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSPI_TO_SPI_BUS(x) ((x) + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_TO_GSPI_BUS(x) ((x) - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (spi_bus == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25862">change 25862</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie8573c4b487394893b467bddccb702d4942a4b87 </div>
<div style="display:none"> Gerrit-Change-Number: 25862 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>