[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Enable CMOS VBNV backup to flash

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/25842


Change subject: soc/amd/stoneyridge: Enable CMOS VBNV backup to flash
......................................................................

soc/amd/stoneyridge: Enable CMOS VBNV backup to flash

Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.

BUG=b:77347873
TEST=Manualy clear CMOS and check coreboot restores VBNV from flash.

Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones at scarletltd.com>
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
2 files changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25842/1

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index e723296..f544796 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -55,6 +55,7 @@
 	select C_ENVIRONMENT_BOOTBLOCK
 	select BOOTBLOCK_CONSOLE
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select RELOCATABLE_MODULES
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select PARALLEL_MP
@@ -72,6 +73,8 @@
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 
 config UDELAY_LAPIC_FIXED_FSB
 	int
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 31dc439..54b1198 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -49,6 +49,7 @@
 bootblock-y += tsc_freq.c
 bootblock-y += southbridge.c
 bootblock-y += nb_util.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
 
 romstage-y += BiosCallOuts.c
 romstage-y += i2c.c
@@ -67,6 +68,7 @@
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 romstage-y += nb_util.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
 
 verstage-y += gpio.c
 verstage-y += i2c.c
@@ -77,6 +79,7 @@
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 verstage-y += tsc_freq.c
 verstage-y += nb_util.c
+verstage-$(CONFIG_SPI_FLASH) += spi.c
 
 postcar-y += monotonic_timer.c
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c

-- 
To view, visit https://review.coreboot.org/25842
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Gerrit-Change-Number: 25842
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180425/994d5bf7/attachment.html>