<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25842">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Enable CMOS VBNV backup to flash<br><br>Now that we have SPI flash writes working, we can support<br>VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve<br>the area in FMAP.<br><br>BUG=b:77347873<br>TEST=Manualy clear CMOS and check coreboot restores VBNV from flash.<br><br>Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88<br>Signed-off-by: Marc Jones <marc.jones@scarletltd.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/Makefile.inc<br>2 files changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25842/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig</span><br><span>index e723296..f544796 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Kconfig</span><br><span>+++ b/src/soc/amd/stoneyridge/Kconfig</span><br><span>@@ -55,6 +55,7 @@</span><br><span>        select C_ENVIRONMENT_BOOTBLOCK</span><br><span>       select BOOTBLOCK_CONSOLE</span><br><span>     select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+   select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH</span><br><span>        select RELOCATABLE_MODULES</span><br><span>   select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span>        select PARALLEL_MP</span><br><span>@@ -72,6 +73,8 @@</span><br><span>       select VBOOT_SEPARATE_VERSTAGE</span><br><span>       select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span>     select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+   select VBOOT_VBNV_CMOS</span><br><span style="color: hsl(120, 100%, 40%);">+        select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH</span><br><span> </span><br><span> config UDELAY_LAPIC_FIXED_FSB</span><br><span>  int</span><br><span>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>index 31dc439..54b1198 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>+++ b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>@@ -49,6 +49,7 @@</span><br><span> bootblock-y += tsc_freq.c</span><br><span> bootblock-y += southbridge.c</span><br><span> bootblock-y += nb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> </span><br><span> romstage-y += BiosCallOuts.c</span><br><span> romstage-y += i2c.c</span><br><span>@@ -67,6 +68,7 @@</span><br><span> romstage-y += tsc_freq.c</span><br><span> romstage-y += southbridge.c</span><br><span> romstage-y += nb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> </span><br><span> verstage-y += gpio.c</span><br><span> verstage-y += i2c.c</span><br><span>@@ -77,6 +79,7 @@</span><br><span> verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span> verstage-y += tsc_freq.c</span><br><span> verstage-y += nb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> </span><br><span> postcar-y += monotonic_timer.c</span><br><span> postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25842">change 25842</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25842"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88 </div>
<div style="display:none"> Gerrit-Change-Number: 25842 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>